{
  "schema_version": "1.0.0",
  "rubric_version": "1.0",
  "license": "CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/)",
  "record": {
    "id": "K-0015",
    "slug": "tamper-evidence",
    "title": "Tamper evidence and tamper resistance",
    "aliases": [
      "tamper evidence",
      "tamper resistance",
      "tamper response",
      "anti-tamper"
    ],
    "status": "draft",
    "last_reviewed": "2026-09-23",
    "review_interval_days": 90,
    "steward": null,
    "provenance": {
      "drafted_by": "ai",
      "reviewed_by": []
    },
    "risk_flags": [],
    "flags": [],
    "one_liner": "Tamper evidence makes interference detectable; tamper resistance makes it difficult or costly; tamper response reacts to it, often by erasing secrets.",
    "sources": [
      {
        "source": "S-1605",
        "supports": "definitions of tamper evidence, tamper detection and tamper response; physical security Levels 2–4; superseded by FIPS 140-3",
        "locator": "§2.1 Glossary; §4.5; CSRC status page"
      },
      {
        "source": "S-1600",
        "supports": "tamper resistant: makes alterations difficult, costly or both (definition written for data)",
        "locator": "term: tamper_resistant (NISTIR 8202)"
      },
      {
        "source": "S-0029",
        "supports": "unlimited physical access can undermine attestation; inspections detect hard-to-hide hardware attacks",
        "locator": "§3.1"
      },
      {
        "source": "S-0035",
        "supports": "flexHEG secure enclosure providing physical tamper protection",
        "locator": "abstract"
      },
      {
        "source": "S-0067",
        "supports": "tamper-evident enclosures named among promising and existing physical security methods for taps and recomputation servers",
        "locator": "physical security measures"
      },
      {
        "source": "S-1317",
        "supports": "94 seals studied; 1–3 low-tech defeats demonstrated for each, 132 in total; mean defeat time 4.3 minutes by one practised person",
        "locator": "abstract; results"
      }
    ],
    "related": [
      "K-0005",
      "K-0007",
      "K-0013"
    ],
    "type": "concept",
    "url": "https://trustbutveri.fyi/concepts/tamper-evidence/",
    "source_file": "content/concepts/tamper-evidence.md",
    "flags_all": [
      "ai-drafted"
    ],
    "body_markdown": "Tamper evidence is an external indication that someone has tried to compromise a device's physical security; tamper resistance makes such attempts difficult, costly or both; and tamper response is an automatic action, at minimum erasing plaintext keys, taken when tampering is detected [[S-1605]] [[S-1600]].\n\nThe US standard for cryptographic modules, FIPS 140-2, since superseded by FIPS 140-3, layers these properties [[S-1605]]:\n- **Level 2** requires evidence of tampering, such as tamper-evident coatings or seals, or pick-resistant locks on covers and doors [[S-1605]].\n- **Level 3** adds detection and response circuitry that zeroizes plaintext secret and private keys when covers or doors are opened [[S-1605]].\n- **Level 4** requires a complete envelope of protection intended to detect and respond to all unauthorized attempts at physical access [[S-1605]].\n\nThese properties matter because the prover usually controls the hardware: Shavit notes that unlimited physical access could undermine a chip's attestation, and relies on inspections to find hardware attacks that damage chips in ways that are hard to hide [[S-0029]]. The flexHEG proposal houses its guarantee processor in a secure enclosure that provides physical tamper protection ([[M-0009]]) [[S-0035]]. For verifier equipment in the prover's facility, such as network taps and recomputation servers, one verification plan names tamper-evident enclosures among promising and existing physical security methods, the subject of [[M-0017|tamper evidence for verifier devices]] [[S-0067]]. Seals can be defeated with simple methods: a 1996 Los Alamos study demonstrated low-tech defeats for each of the 94 passive and electronic seals it examined, with a mean defeat time of 4.3 minutes for one practised person [[S-1317]].",
    "body_text": "Tamper evidence is an external indication that someone has tried to compromise a device's physical security; tamper resistance makes such attempts difficult, costly or both; and tamper response is an automatic action, at minimum erasing plaintext keys, taken when tampering is detected [S-1605] [S-1600]. The US standard for cryptographic modules, FIPS 140-2, since superseded by FIPS 140-3, layers these properties [S-1605]: - Level 2 requires evidence of tampering, such as tamper-evident coatings or seals, or pick-resistant locks on covers and doors [S-1605]. - Level 3 adds detection and response circuitry that zeroizes plaintext secret and private keys when covers or doors are opened [S-1605]. - Level 4 requires a complete envelope of protection intended to detect and respond to all unauthorized attempts at physical access [S-1605]. These properties matter because the prover usually controls the hardware: Shavit notes that unlimited physical access could undermine a chip's attestation, and relies on inspections to find hardware attacks that damage chips in ways that are hard to hide [S-0029]. The flexHEG proposal houses its guarantee processor in a secure enclosure that provides physical tamper protection (Hardware-enabled guarantees (flexHEG) and guarantee processors) [S-0035]. For verifier equipment in the prover's facility, such as network taps and recomputation servers, one verification plan names tamper-evident enclosures among promising and existing physical security methods, the subject of tamper evidence for verifier devices [S-0067]. Seals can be defeated with simple methods: a 1996 Los Alamos study demonstrated low-tech defeats for each of the 94 passive and electronic seals it examined, with a mean defeat time of 4.3 minutes for one practised person [S-1317].",
    "referenced_by": [
      {
        "id": "M-0019",
        "title": "Chip registries and manufacturing records",
        "url": "https://trustbutveri.fyi/mechanisms/chip-registries-and-manufacturing-records/"
      },
      {
        "id": "M-0009",
        "title": "Hardware-enabled guarantees (flexHEG) and guarantee processors",
        "url": "https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/"
      },
      {
        "id": "M-0017",
        "title": "Tamper evidence for verifier devices",
        "url": "https://trustbutveri.fyi/mechanisms/tamper-evidence-for-verifier-devices/"
      },
      {
        "id": "M-0008",
        "title": "TEE remote attestation for AI workloads",
        "url": "https://trustbutveri.fyi/mechanisms/tee-remote-attestation/"
      },
      {
        "id": "I-0012",
        "title": "Low-trust AI compute verification system overview",
        "url": "https://trustbutveri.fyi/implementations/low-trust-compute-verification-system-overview/"
      },
      {
        "id": "I-0010",
        "title": "RAND secure inference data center (SIDC) design",
        "url": "https://trustbutveri.fyi/implementations/rand-secure-inference-data-centers/"
      },
      {
        "id": "C-0002",
        "title": "Chips are where they are declared to be",
        "url": "https://trustbutveri.fyi/claims/chips-are-where-declared/"
      },
      {
        "id": "K-0007",
        "title": "Hardware-enabled mechanism (HEM)",
        "url": "https://trustbutveri.fyi/concepts/hardware-enabled-mechanism/"
      },
      {
        "id": "K-0005",
        "title": "Root of trust",
        "url": "https://trustbutveri.fyi/concepts/root-of-trust/"
      },
      {
        "id": "K-0013",
        "title": "Side channel",
        "url": "https://trustbutveri.fyi/concepts/side-channel/"
      }
    ]
  }
}