# AI verification proposal

A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-09. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0004,M-0010,M-0008&chips=existing

How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's development status, security evidence and findings. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and findings) and https://trustbutveri.fyi/about/readiness/ (development status).

## Filters

Filters apply to mechanisms only and describe the setting the proposal is for.

- **Chips: Existing chips only.** "Existing chips only" removes mechanisms that need changes to future chip designs. New chip features take years to reach a deployed fleet and cover only chips made after they ship. Mechanisms that use shipping features, such as trusted execution environments or performance counters, stay.

23 of 25 mechanisms on the map pass these filters.

## Overview

One row per mechanism, read from its record. Open failures: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees. Findings are grouped as known failures, scope limitations and open questions. Only known failures count as failures. Counts are an inventory of published findings, not a risk score.

| Mechanism | Development | Security evidence | Prover | Attack testing | Hardware | Open failures | Weights | Inputs and outputs | Training data |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Zero-knowledge proofs of inference | Research demonstration | Published attack testing | Adversarial | Independent red-team | None | 0 / 0 / 0 | hidden | shown | not involved |
| On-chip telemetry from timing, memory and performance counters | Research demonstration | Published attack testing | Semi-trusted | Red-teamed | Existing features | 0 / 2 / 0 | depends | depends | depends |
| TEE remote attestation for AI workloads | Operational use | Published attack testing | Semi-trusted | Independent red-team | Existing features | 2 / 3 / 0 | hidden | hidden | hidden |

## Claims

No claims chosen.

## Mechanisms

### Zero-knowledge proofs of inference

A prover produces a cryptographic proof that an output came from running a committed model on a given input, without revealing the weights. ([Zero-knowledge proofs of inference](https://trustbutveri.fyi/mechanisms/zk-proofs-of-inference/))

- Assessment: mechanism family.
- Development: Research demonstration (legacy code R2), assessed for proving a language model's output follows from committed weights, against a cheating prover.
- Security evidence: Published attack testing. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: none. Prover cooperation: required. Attack testing: independent red-team. Category: Cryptographic & computational.
- What the verifier sees: model weights hidden; inputs and outputs shown; training data not involved. The weights stay committed and hidden; the verifier knows each input and output it checks.

### On-chip telemetry from timing, memory and performance counters

Uses on-chip measurements, such as task timings, whether data sits in chip memory, and performance counters, as evidence of what AI chips are running. ([On-chip telemetry from timing, memory and performance counters](https://trustbutveri.fyi/mechanisms/on-chip-telemetry/))

- Assessment: mechanism family.
- Development: Research demonstration (legacy code R2), assessed for workload evidence from GPU counters and timing, assuming authentic measurements.
- Security evidence: Published attack testing. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: semi-trusted prover. Hardware: existing features. Prover cooperation: partial. Attack testing: red-teamed. Category: On-chip & hardware-enabled.
- What the verifier sees: model weights depends; inputs and outputs depends; training data depends. Counters do not read weights or data, but richer counters can leak secrets through side channels.

### TEE remote attestation for AI workloads

Trusted execution environments (TEEs) in CPUs and GPUs sign reports of launched software, so remote verifiers can check which code an AI workload started with. ([TEE remote attestation for AI workloads](https://trustbutveri.fyi/mechanisms/tee-remote-attestation/))

- Assessment: mechanism family.
- Development: Operational use (legacy code R3), assessed for showing which software ran to a party that distrusts the operator holding the hardware.
- Security evidence: Published attack testing. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: semi-trusted prover. Hardware: existing features. Prover cooperation: required. Attack testing: independent red-team. Category: On-chip & hardware-enabled.
- What the verifier sees: model weights hidden; inputs and outputs hidden; training data hidden. The enclave keeps what runs inside it from the host and the verifier; the verifier sees signed measurements. This relies on the chip vendor's hardware.


## Properties

**Operational use**

- TEE remote attestation for AI workloads: Operational use (legacy code R3), assessed for showing which software ran to a party that distrusts the operator holding the hardware

**Built for an adversarial prover**

- Zero-knowledge proofs of inference

**No new hardware needed**

- Zero-knowledge proofs of inference
- On-chip telemetry from timing, memory and performance counters
- TEE remote attestation for AI workloads

**Failures since mitigated**

- Software-only forgery of SEV-SNP attestation (RMPocalypse, Fabricked) (in TEE remote attestation for AI workloads) [29][30][34][35]


## Attack testing

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

**Testing history**

- Zero-knowledge proofs of inference: Independent red-team
- On-chip telemetry from timing, memory and performance counters: Red-teamed
- TEE remote attestation for AI workloads: Independent red-team


## Limits

**Open critical failures**

- DDR5 memory-bus interposers forge Intel TDX attestations and break SEV-SNP protections (TEE.fail, DDRop) (known failure, demonstrated attack, in TEE remote attestation for AI workloads; https://trustbutveri.fyi/mechanisms/tee-remote-attestation/evidence/flaws/1/) [16][19][21][22][27][29][33][34]. Mechanism-class evidence. Critical when the verifier must resist physical access plus host control on the affected DDR5 platforms. The Intel demonstrations defeat attestation; TEE.fail's AMD demonstration extracts a guest key, not an AMD attestation key. These results do not cover every TEE architecture. Independent researchers placed an interposer, built for under $1000, on the DDR5 memory bus of servers running Intel TDX and AMD SEV-SNP. Server TEEs encrypt memory deterministically, without integrity or freshness protection, and the researchers exploited this to recover secrets. The attack needs physical access and root privileges.
  - On Intel, they extracted the provisioning certification key from a machine that Intel's service rated fully up to date. This per-CPU key signs the keys used in SGX and TDX attestation. With it they forged SGX and TDX attestations.
  - On AMD SEV-SNP with ciphertext hiding enabled, they recovered an ECDSA private key used by OpenSSL inside the virtual machine. It was not an AMD attestation key. Other independent attacks did break SEV-SNP attestation. Battering RAM did so with a DDR4 interposer, and RMPocalypse and Fabricked from malicious host software.

  A second team, from KU Leuven, ETH Zurich, Durham University and Google, built DDRop, an active DDR5 interposer with a bill of materials of $159. It silently drops memory writes, which memory encryption without freshness protection cannot detect. With brief physical access and control of the host software and BIOS, the researchers forced trust domains into debug mode and forged attestation reports on an up-to-date Intel TDX platform. The same primitive breaks the integrity of Scalable SGX and SEV-SNP, though the authors report no SEV-SNP attestation forgery.

  The TEE.fail authors report that Intel and AMD consider interposer attacks out of scope, which leaves physical security as the only mitigation. The DDRop authors report the same position, and that both vendors issued security advisories on disclosure in September 2026. PAL*M lists this attack class as out of its scope, and Tinfoil's documentation acknowledges it. Gloria Z calls key extraction through bus interposition "relatively low-hanging fruit" in an international treaty scenario.

  Related mechanism: Hardware-enabled guarantees (flexHEG) and guarantee processors (R1, not in the proposal). A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
- DDR4 memory-bus interposers forge SGX and SEV-SNP attestation (Battering RAM, WireTap) (known failure, demonstrated attack, in TEE remote attestation for AI workloads; https://trustbutveri.fyi/mechanisms/tee-remote-attestation/evidence/flaws/2/) [27][28]. Mechanism-class evidence. Critical for the tested DDR4 SGX and SEV-SNP configurations against a physical host attacker. The authors exclude DDR5 from these demonstrations, including TDX servers; the DDR5 attacks have a separate finding. Two independent teams broke server TEE attestation on DDR4 memory with interposers they built themselves. Both attacks need physical access to install the device and root privileges on the host.
  - Battering RAM, by researchers at KU Leuven and the Universities of Birmingham and Durham, uses an interposer with a bill of materials of $47.62. It creates memory aliases at runtime, which bypasses the boot-time alias checks that AMD and Intel introduced against static aliasing attacks such as BadRAM. On Intel Scalable SGX it gained arbitrary read and write access to enclave plaintext and extracted SGX's platform provisioning key, which lets an attacker forge attestation certificates for arbitrary quoting enclaves. On up-to-date AMD SEV-SNP servers it captured the launch digests of genuine VMs and replayed them into modified VMs, so that backdoored VMs pass attestation.
  - WireTap, by researchers at Purdue University and Georgia Tech, uses an interposer built for under $1000 that records DDR4 bus traffic. On a Xeon Scalable server in fully trusted status it recovered the ECDSA attestation key of SGX's Quoting Enclave in 45 minutes and forged SGX quotes. The authors then showed end-to-end attacks on SGX-based blockchain deployments.

  Both attacks are limited to DDR4 systems. The Battering RAM authors state that all commercial TDX machines use DDR5, and the WireTap authors state that 4th and 5th generation Xeon Scalable processors need DDR5 and are not affected by their current work. According to the Battering RAM authors, Intel and AMD acknowledged the findings but consider physical attacks on DRAM out of scope for their current products. The WireTap authors report that Intel considers their attack outside the SGX threat model, and that there is no mitigation besides running servers in secure physical environments.

  Related mechanism: Hardware-enabled guarantees (flexHEG) and guarantee processors (R1, not in the proposal). A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.

**Open significant failures**

- Adversarially disguised fine-tuning partly evades classification (known failure, demonstrated attack, in On-chip telemetry from timing, memory and performance counters; https://trustbutveri.fyi/mechanisms/on-chip-telemetry/evidence/flaws/2/) [15]. Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware.
- Counters leak information about protected workloads (known failure, theoretical argument, in On-chip telemetry from timing, memory and performance counters; https://trustbutveri.fyi/mechanisms/on-chip-telemetry/evidence/flaws/4/) [16][17]. Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality.
- H100 attestation not bound to a specific confidential VM (known failure, demonstrated attack, in TEE remote attestation for AI workloads; https://trustbutveri.fyi/mechanisms/tee-remote-attestation/evidence/flaws/4/) [21]. Mechanism-class evidence. The demonstration combines a genuine H100 report with forged Intel TDX evidence. It depends on the CPU attestation already being defeated; a GPU report alone does not demonstrate that an intact CPU-to-GPU trust chain was bypassed. The TEE.fail authors fetched genuine H100 confidential-computing attestations from a rented server running their TDX VM. They combined these with forged TDX quotes. A proxy running outside any TEE then passed both the TDX and the GPU attestation checks. The authors attribute this to NVIDIA not binding the H100 to the identities of specific VMs. Their site states more generally that NVIDIA's attestation reports are not bound to a specific confidential VM or CPU. Intel, AMD, NVIDIA and the affected deployments acknowledged the findings, according to the authors, and the affected deployments were working on mitigations. The attack does not target NVIDIA's confidential-computing components directly, so the authors state that there are no mitigations on the NVIDIA side.
- Side channels and other attacks by the host on CPU and GPU TEEs (known failure, demonstrated attack, in TEE remote attestation for AI workloads; https://trustbutveri.fyi/mechanisms/tee-remote-attestation/evidence/flaws/5/) [16][18][19][36][37]. Mechanism-class evidence. The cited studies concern particular CPU and GPU platforms and attack prerequisites. StackWarp has AMD microcode patches; the open class-level entry does not mean every cited defect is unmitigated or applies to every TEE-backed implementation. PAL*M and Attestable Audits cite published side-channel, single-stepping, interrupt-injection and memory-aliasing attacks on Intel TDX and AMD SEV, including T-Time, TDXploit, CIPHER-LEAKS, Heckler and BadRAM. PAL*M treats them as out of scope. Attestable Audits proposes revoking vulnerable enclave images. Gloria Z notes that performance counters have themselves been used as a side channel, for example in CounterSEVeillance. New attacks of this kind continue to appear. In StackWarp, researchers at CISPA showed that a malicious hypervisor can shift the stack pointer of an SEV-SNP guest on AMD Zen 1 to Zen 5 processors with simultaneous multithreading enabled, which fully breaks the guest's integrity. AMD released microcode patches. On the GPU side, an independent analysis of NVIDIA's confidential computing by IBM Research and Ohio State University found that bulk command and data transfers are protected, but some metadata, timing behaviour and coordination signals remain in unprotected shared memory. The authors report that these can reveal computational behaviour and in some cases allow manipulation of operations. They disclosed the findings to NVIDIA.
- Root of trust concentrated in a few hardware vendors (known failure, theoretical argument, in TEE remote attestation for AI workloads; https://trustbutveri.fyi/mechanisms/tee-remote-attestation/evidence/flaws/8/) [16][18][40][41]. Mechanism-class evidence. Vendor trust is an assumption of the attestation chain. The root-seed extraction study concerns AMD EPYC Milan and firmware downgrade with privileged host and platform-flash access; it is not evidence of the same failure on Intel, NVIDIA or all AMD generations. The root of trust is the certificate authorities of a small number of vendors (AMD, Intel and NVIDIA), which generate the keys and fuse them onto the chips. Gloria Z notes that whoever has access to a hardware key, or can certify one, can in principle produce valid reports for arbitrary measurements without the physical chip. Attestable Audits notes that the approach holds only "as long as the vendor of the secure hardware is trusted". A 2026 preprint reports that a host with root control and the ability to rewrite platform flash can downgrade an AMD EPYC Milan processor to legacy security-processor firmware and extract the hardware root seed from which SEV-SNP attestation keys are derived. The authors state that this lets them forge attestation reports for any firmware version. AMD describes the firmware-loader flaw the attack starts from as a legacy attack mitigated in 2021.

**Scope limitations**

- The proof covers a fixed-point approximation, not the floating-point model (scope limitation, open question, in Zero-knowledge proofs of inference; https://trustbutveri.fyi/mechanisms/zk-proofs-of-inference/evidence/flaws/1/) [1][5][7][11]. Current ZK inference systems prove a quantised version of the network. zkLLM scales values by 2^16 and reports small perplexity changes. Attestable reports quantising matrix multiplications to 8-bit integers while proving other operations in floating point. A verifier therefore learns about the proof-friendly variant, and must separately accept that this variant is the declared model. Trail of Bits built a ResNet-18 backdoor that is dormant in the full-precision model and active after ezkl's quantisation; whether it persists through proving was left for further investigation. A verification system design notes that ZKPs can emulate floating-point operations. Rounding makes floating-point results depend on summation order, so bit-for-bit replay of an accelerator's results needs its original reduction tree. The report calls emulating that tree inside a ZKP an open, intricate problem and asks what it would cost.
- A proof speaks only for the computations that were proven (scope limitation, theoretical argument, in Zero-knowledge proofs of inference; https://trustbutveri.fyi/mechanisms/zk-proofs-of-inference/evidence/flaws/2/) [12]. Attestable writes that "a proof of some computation is not a proof of all computation", and that a proof cannot discover a datacenter that was never declared. Proofs of inference do not by themselves show that no other workload ran on the same or other hardware.

  Related mechanism: Proofs of useful work for capacity accounting (R1, not in the proposal). The record names proof-of-work accounting as the kind of compute accounting needed to show that proven inference was the only work done.
- The model architecture is disclosed (scope limitation, theoretical argument, in Zero-knowledge proofs of inference; https://trustbutveri.fyi/mechanisms/zk-proofs-of-inference/evidence/flaws/3/) [1][3]. ZKML "requires that the model architecture (but not weights) is revealed", and zkLLM assumes a publicly known model structure. Architecture can be commercially sensitive.
- Proofs do not bind computational effort (Hollow-LLM) (scope limitation, demonstrated attack, in Zero-knowledge proofs of inference; https://trustbutveri.fyi/mechanisms/zk-proofs-of-inference/evidence/flaws/4/) [10]. Researchers at the University of Southern California show that a proof of inference certifies that an output is consistent with committed weights under the declared architecture, but not how much computation produced it. In their Hollow-LLM attack, a provider keeps the declared architecture and parameter count but commits to "ghost weights". Some layers pass their inputs through unchanged, and wide layers carry the signal in a small subspace, so a much smaller inner model does the real work. The ghost weights satisfy the verification circuit and yield valid proofs.

  The authors ran the attack with the proof procedure of zkGPT, a separate ZK inference system, on a 6-layer, 512-dimensional transformer declared as up to 12 layers and 1,024 dimensions. Outputs were identical to the inner model's, and serving cost stayed at the inner model's level. An honest model of the declared size cost 2.4 times as much to prefill and 3.1 times as much to decode. Proving cost still grew with the declared architecture.

  The authors note that results may be served before any proof, with the provider building the witness only when a call is selected for audit. They describe their constructions as "compatible with state-of-the-art zkLLM pipelines", and state that the attack does not imply a flaw in the proof system itself. They propose challenge-based audits and ablation tests, which raise the cost of cheating but give no guarantee.
- Software-read telemetry can be forged by the operator (scope limitation, theoretical argument, in On-chip telemetry from timing, memory and performance counters; https://trustbutveri.fyi/mechanisms/on-chip-telemetry/evidence/flaws/1/) [13][15]. NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized.

  Related mechanism: Hardware-enabled guarantees (flexHEG) and guarantee processors (R1, not in the proposal). A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing.
- Timing challenges do not identify the individual chip (scope limitation, theoretical argument, in On-chip telemetry from timing, memory and performance counters; https://trustbutveri.fyi/mechanisms/on-chip-telemetry/evidence/flaws/3/) [13]. GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use.
- Attestation covers launch state, and measurements can be incomplete (scope limitation, theoretical argument, in TEE remote attestation for AI workloads; https://trustbutveri.fyi/mechanisms/tee-remote-attestation/evidence/flaws/6/) [16][31][32][38][39]. Mechanism-class evidence. A general measurement-boundary limitation. The concrete WhatsApp configuration findings were fixed before launch; Apple's research-environment configuration flaw was also fixed. Their fixes do not remove the need to bind each deployment's runtime inputs. Attestation measures launch state, not runtime state. Data loaded later, such as model weights, must be bound separately. Gloria Z argues that gaps in measuring feature flags, environment variables and invocation arguments are "perhaps the most likely failure mode". She also warns that a badly designed hashing scheme could let two models with significantly different properties share a hash "without breaking the hash function itself". Independent reviews of production systems have found such gaps. In WhatsApp's deployment, Trail of Bits found environment variables and ACPI tables loaded outside the measurement, and rated both high severity. Meta fixed them. On an Apple PCC node running in Apple's research environment, a researcher reports that tampered configuration files left the attestation unchanged.
- Deployment-level attestation does not cover the whole chip (scope limitation, theoretical argument, in TEE remote attestation for AI workloads; https://trustbutveri.fyi/mechanisms/tee-remote-attestation/evidence/flaws/7/) [16]. Mechanism-class evidence. A limitation of deployment-level evidence when the claim concerns all activity on a chip. It does not defeat a narrower claim about which software served one attested request. An attestation shows what one confidential VM runs. It does not show what else the hypervisor runs on the same hardware. Gloria Z calls the difference between deployment-level attestation and chip-wide monitoring "the gaping hole in this plan". This matters most for negative claims such as the absence of training.

  Related mechanism: On-chip telemetry from timing, memory and performance counters (R2, in the proposal). On-chip counters are a proposed route to evidence about everything a chip runs, which attestation of one workload does not give.

**Open questions**

- No quantified error rates or formal thresholds for timing primitives (open question, open question, in On-chip telemetry from timing, memory and performance counters; https://trustbutveri.fyi/mechanisms/on-chip-telemetry/evidence/flaws/5/) [13]. Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work.


## Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open failure or a dependency. Pointers, not recommendations: each brings its own readiness level and findings, and none is claimed to close a failure.

- **Proofs of useful work for capacity accounting** (Proposed (legacy code R1), assessed for bounding the spare capacity of declared hardware that could run training)
  - Zero-knowledge proofs of inference waits on it: Showing that proven inference was the only work done needs a compute-accounting mechanism such as proof-of-work accounting, which is only proposed.
- **Hardware-enabled guarantees (flexHEG) and guarantee processors** (Proposed (legacy code R1), assessed for checking and enforcing training-compute limits on chips, against adversaries up to states). Excluded by the filters: needs new chips
  - Bears on the open critical failure "DDR5 memory-bus interposers forge Intel TDX attestations and break SEV-SNP protections (TEE.fail, DDRop)" in TEE remote attestation for AI workloads. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
  - Bears on the open critical failure "DDR4 memory-bus interposers forge SGX and SEV-SNP attestation (Battering RAM, WireTap)" in TEE remote attestation for AI workloads. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
  - On-chip telemetry from timing, memory and performance counters waits on it: Shipping accelerators need a tamper-resistant, authenticated telemetry path.
  - TEE remote attestation for AI workloads waits on it: Vendor threat models exclude sophisticated physical attacks, but in international verification the prover holds the hardware.


## Dependencies

**Shared foundations**

- Hardware-enabled guarantees (flexHEG) and guarantee processors, relied on by On-chip telemetry from timing, memory and performance counters and TEE remote attestation for AI workloads

**Blockers**

- Zero-knowledge proofs of inference: Proving takes about 13 minutes (803 seconds) per 2,048-token forward pass of a 13B model on one A100, and a verification system design calls the overhead heavy. (performance & compatibility) [1][11]
- Zero-knowledge proofs of inference: ZKML and zkLLM prove fixed-point arithmetic, and a verification system design calls emulating an accelerator's original floating-point reduction tree inside a zero-knowledge proof, which bit-for-bit replay needs, an open and intricate problem whose cost is also unsettled. (performance & compatibility) [1][3][11]
- Zero-knowledge proofs of inference: zkLLM's code is unaudited, interactive and archived; the one audited ZK inference library, ezkl, had high-severity circuit soundness bugs before its fixes. (adversarial validation) [2][7]
- Zero-knowledge proofs of inference: Showing that proven inference was the only work done needs a compute-accounting mechanism such as proof-of-work accounting, which is only proposed. (coverage & hidden compute; waits on Proofs of useful work for capacity accounting) [12]
- On-chip telemetry from timing, memory and performance counters: Shipping accelerators need a tamper-resistant, authenticated telemetry path. (hardware trust; waits on Hardware-enabled guarantees (flexHEG) and guarantee processors) [14][15]
- On-chip telemetry from timing, memory and performance counters: NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. (privacy & leakage) [16][17]
- On-chip telemetry from timing, memory and performance counters: Continuous challenge puzzles cost power and throughput on production workloads. (performance & compatibility) [13]
- On-chip telemetry from timing, memory and performance counters: Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. (adversarial validation) [15]
- TEE remote attestation for AI workloads: Vendor threat models exclude sophisticated physical attacks, but in international verification the prover holds the hardware. (hardware trust; waits on Hardware-enabled guarantees (flexHEG) and guarantee processors) [17][21][27][28][33][42]
- TEE remote attestation for AI workloads: Negative claims such as "no undeclared training" need chip-wide accounting of all workloads, which attestation does not provide. (coverage & hidden compute; waits on On-chip telemetry from timing, memory and performance counters) [16]
- TEE remote attestation for AI workloads: Multi-GPU and multi-node coverage is incomplete, because Hopper leaves NVLink traffic unencrypted and NVIDIA's April 2026 release notes list no multi-node confidential mode. (performance & compatibility) [17][43]
- TEE remote attestation for AI workloads: Rival parties have not agreed on trust roots and key provenance they would accept. (access & governance) [16]
- TEE remote attestation for AI workloads: CPU-only enclaves are costly for large models, because in the Attestable Audits prototype CPU inference cost 21.7 times as much per token as GPU inference and the enclave roughly doubled the CPU cost. (performance & compatibility) [18]


## What the verifier sees

- Model weights: shown by none; depends on the design for On-chip telemetry from timing, memory and performance counters; hidden by Zero-knowledge proofs of inference and TEE remote attestation for AI workloads; not involved in none; unspecified for none.
- Inputs and outputs: shown by Zero-knowledge proofs of inference; depends on the design for On-chip telemetry from timing, memory and performance counters; hidden by TEE remote attestation for AI workloads; not involved in none; unspecified for none.
- Training data: shown by none; depends on the design for On-chip telemetry from timing, memory and performance counters; hidden by TEE remote attestation for AI workloads; not involved in Zero-knowledge proofs of inference; unspecified for none.

## Implementations

- Zero-knowledge proofs of inference: [Attestable zero-knowledge inference prover](https://trustbutveri.fyi/implementations/attestable-zk-inference/) (R1, product); [EZKL](https://trustbutveri.fyi/implementations/ezkl/) (R2, product); [Low-trust AI compute verification system overview](https://trustbutveri.fyi/implementations/low-trust-compute-verification-system-overview/) (R1, proposed architecture); [zkLLM](https://trustbutveri.fyi/implementations/zkllm/) (R2, research prototype)
- On-chip telemetry from timing, memory and performance counters: none on the map
- TEE remote attestation for AI workloads: [Apple Private Cloud Compute](https://trustbutveri.fyi/implementations/apple-private-cloud-compute/) (R3, product); [Attestable Audits](https://trustbutveri.fyi/implementations/attestable-audits/) (R2, research prototype); [Cove](https://trustbutveri.fyi/implementations/cove/) (R2, open-source project); [PAL*M](https://trustbutveri.fyi/implementations/palm/) (R2, research prototype); [Tinfoil model identity (Modelwrap)](https://trustbutveri.fyi/implementations/tinfoil-model-identity/) (R3, product)

## Sources

1. zkLLM: Zero Knowledge Proofs for Large Language Models, H. Sun et al. (2024). https://doi.org/10.1145/3658644.3670334
2. zkllm-ccs2024: code for zkLLM: Zero Knowledge Proofs for Large Language Models, H. Sun (2024). https://github.com/jvhs0706/zkllm-ccs2024
3. ZKML: An Optimizing System for ML Inference in Zero-Knowledge Proofs, B.-J. Chen et al. (2024). https://doi.org/10.1145/3627703.3650088
4. NanoZK: Privacy-Preserving Verifiable Inference for Large Language Models via Layerwise Zero-Knowledge Proofs, Z. Wang (2026). https://arxiv.org/abs/2603.18046
5. Proving LLMs at Scale, Attestable (2026). https://attestable.com/blog/proving-llms-scale
6. Verifiable evaluations of machine learning models using zkSNARKs, T. South et al. (2024). https://arxiv.org/abs/2402.02675
7. Zkonduit EZKL Security Assessment, F. Casal et al. (2025). https://github.com/trailofbits/publications/blob/master/reviews/2025-03-zkonduit-ezkl-securityreview.pdf
8. DeepProve-1: The First zkML System to Prove a Full LLM Inference, Lagrange Labs (2025). https://lagrange.dev/blog/deepprove-1
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