# AI verification proposal

A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-08. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0017,M-0003,M-0002&chips=existing

How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's readiness and open flaws. Readiness levels R0 to R4 describe one record's public evidence for its assessed use and are never combined. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and flaws) and https://trustbutveri.fyi/about/readiness/ (readiness levels).

## Filters

Filters apply to mechanisms only and describe the setting the proposal is for.

- **Chips: Existing chips only.** "Existing chips only" removes mechanisms that need changes to future chip designs. New chip features take years to reach a deployed fleet and cover only chips made after they ship. Mechanisms that use shipping features, such as trusted execution environments or performance counters, stay.

23 of 25 mechanisms on the map pass these filters.

## Overview

One row per mechanism, read from its record. Open flaws: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees.

| Mechanism | Readiness | Prover | Attack testing | Hardware | Open flaws | Weights | Inputs and outputs | Training data |
| --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Tamper evidence for verifier devices | R2 | Adversarial | Analysis | Retrofit device | 0 / 3 / 0 | not involved | not involved | not involved |
| Whole-workload recomputation (reproducible packets) | R1 | Adversarial | None | Retrofit device | 0 / 2 / 0 | depends | depends | depends |
| Deterministic and bit-exact inference | R3 | Adversarial | Analysis | None | 0 / 1 / 1 | depends | depends | not involved |

## Claims

No claims chosen.

## Mechanisms

### Tamper evidence for verifier devices

Enclosures, seals and sensors that make physical interference with verification hardware either visible or self-defeating. ([Tamper evidence for verifier devices](https://trustbutveri.fyi/mechanisms/tamper-evidence-for-verifier-devices/))

- Assessment: mechanism family.
- Readiness: R2 Demonstrated, assessed for detecting probing of proposed verifier hardware, using server and electronics prototypes as evidence.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: retrofit device. Prover cooperation: partial. Attack testing: analysis. Category: Off-chip devices & sensors.
- What the verifier sees: model weights not involved; inputs and outputs not involved; training data not involved. Protects verifier devices; it does not handle model data.

### Whole-workload recomputation (reproducible packets)

Organizing all AI workloads in a facility into discrete, reproducible units, so that a verifier can recompute a random sample and check each one. ([Whole-workload recomputation (reproducible packets)](https://trustbutveri.fyi/mechanisms/reproducible-computation-packets/))

- Assessment: mechanism family.
- Readiness: R1 Proposed, assessed for recomputing whole workloads to show a cluster runs only declared inference.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: retrofit device. Prover cooperation: required. Attack testing: none. Category: Isolation & system architectures.
- What the verifier sees: model weights depends; inputs and outputs depends; training data depends. Recomputing sampled units needs weights and sampled inputs or training data inside the checking environment. The design depends on securing that environment; disclosure depends on its confidentiality boundary.

### Deterministic and bit-exact inference

Making model inference reproducible bit for bit, so that a verifier's re-run must match the provider's output exactly rather than approximately. ([Deterministic and bit-exact inference](https://trustbutveri.fyi/mechanisms/deterministic-inference/))

- Assessment: mechanism family.
- Readiness: R3 In production, assessed for reproducing open-model inference from receipts in Gensyn's information-market service.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: none. Prover cooperation: required. Attack testing: analysis. Category: Cryptographic & computational.
- What the verifier sees: model weights depends; inputs and outputs depends; training data not involved. Exact replay needs the weights, configuration and replayed requests inside the recomputation environment. What the verifier sees depends on whether that environment keeps them confidential.


## Properties

**In production**

- Deterministic and bit-exact inference: R3 In production, assessed for reproducing open-model inference from receipts in Gensyn's information-market service

**Built for an adversarial prover**

- Tamper evidence for verifier devices
- Whole-workload recomputation (reproducible packets)
- Deterministic and bit-exact inference

**No new hardware needed**

- Deterministic and bit-exact inference


## Attack testing

Published attempts to break a system, including those that found failures. Testing history does not establish that open flaws are resolved.

**Testing history**

- Tamper evidence for verifier devices: Analysis
- Deterministic and bit-exact inference: Analysis


## Limits

**Open significant flaws**

- Seals are often defeated with simple methods (demonstrated attack, in Tamper evidence for verifier devices; https://trustbutveri.fyi/mechanisms/tamper-evidence-for-verifier-devices/#flaw-1) [8][9]. Mechanism-class evidence. Published defeats of general security seals. They warn about proposed verifier-device seals, but do not demonstrate defeat of an AI verification enclosure or sensor. In 1996 a Los Alamos vulnerability assessment defeated all 94 security seals it examined, with 132 defeats in total, using rapid, inexpensive, low-tech methods. It found that seal cost did not predict security. In 2001 Johnston reported that high-tech seals are often easier to defeat than low-tech ones.
- Security depends on inspection protocols (theoretical argument, in Tamper evidence for verifier devices; https://trustbutveri.fyi/mechanisms/tamper-evidence-for-verifier-devices/#flaw-2) [6][9]. Mechanism-class evidence. An inspection and protocol requirement drawn from safeguards and enclosure studies, not a reported break of a deployed AI verifier. Johnston argues that a seal is no better than the protocols for using it, and that inspectors are usually given little useful information on how to detect tampering. The Sandia survey notes that larger enclosures are hard to inspect fully and that sensor data must be authenticated.
- Attack classes outside published models (open question, in Tamper evidence for verifier devices; https://trustbutveri.fyi/mechanisms/tamper-evidence-for-verifier-devices/#flaw-3) [1][2][10]. Mechanism-class evidence. The radio compensation result is emulated using measured channel data under a known-reference attacker model. It is not a physical bypass demonstration against an AI verifier enclosure. The authors of the batteryless cover say they cannot assess chemical-solvent attacks, which exceed their expertise, and deem cover removal impractical. Anti-Tamper Radio's reference can drift as the environment or measurement system ages; the authors suggest gradually renewing the reference. A 2025 follow-up by some of the same authors shows, by emulation on measured channel data, that an attacker who knows the reference channel and the needle's effect on it could inject a signal that cancels the change caused by a needle insertion. It proposes a reconfigurable intelligent surface that randomizes the channel as a countermeasure.
- Spare compute is outside the scheme (theoretical argument, in Whole-workload recomputation (reproducible packets); https://trustbutveri.fyi/mechanisms/reproducible-computation-packets/#flaw-1) [11][12]. The plan states that it does not verify that spare compute is not used for unapproved workloads, because this seems very challenging. Recomputation checks the correctness of declared work, not its completeness.

  Related mechanism: Proofs of useful work for capacity accounting (R1, not in the proposal). Proposed as one input to accounting for spare capacity on declared hardware.
- Non-compliant work could be encoded inside compliant-looking packets (theoretical argument, in Whole-workload recomputation (reproducible packets); https://trustbutveri.fyi/mechanisms/reproducible-computation-packets/#flaw-2) [11]. The plan notes that an AI company might try to encode a non-compliant workload inside a workload that looks compliant on the surface.
- Cross-hardware replay relies on reverse-engineered, closed behaviour (open question, in Deterministic and bit-exact inference; https://trustbutveri.fyi/mechanisms/deterministic-inference/#flaw-2) [17][19]. Emulating one GPU's rounding on another requires reverse-engineering tensor-core arithmetic and modelling proprietary kernel choices. Hawkeye covers a subset of NVIDIA architectures and states that attention and other higher-level operations need further reverse engineering. For the bit-exact emulator, a proprietary Hopper kernel family is an open edge case.

**Open minor flaws**

- Some kernels remain genuinely nondeterministic (open question, in Deterministic and bit-exact inference; https://trustbutveri.fyi/mechanisms/deterministic-inference/#flaw-1) [17]. The bit-exact work separates kernels that are deterministic but not batch-invariant from truly nondeterministic ones that use atomic functions. Some integer de-quantization kernels use atomic additions and remain nondeterministic, so exact replay needs backends that avoid them.

**Not yet demonstrated**

- Whole-workload recomputation (reproducible packets): R1 Proposed, assessed for recomputing whole workloads to show a cluster runs only declared inference


## Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open flaw or a dependency. Pointers, not recommendations: each brings its own readiness level and flaws, and none is claimed to close a flaw.

- **Proofs of useful work for capacity accounting** (R1 Proposed, assessed for bounding the spare capacity of declared hardware that could run training)
  - Bears on the open significant flaw "Spare compute is outside the scheme" in Whole-workload recomputation (reproducible packets). Proposed as one input to accounting for spare capacity on declared hardware.
- **Network taps and certifiers** (R1 Proposed, assessed for committing a complete record of cluster traffic, so declared inference can be checked)
  - Whole-workload recomputation (reproducible packets) waits on it: All traffic must reach the recomputation server via network taps, and the server's integrity is critical.


## Dependencies

**Missing prerequisites**

- Network taps and certifiers (R1 Proposed, assessed for committing a complete record of cluster traffic, so declared inference can be checked), needed by Whole-workload recomputation (reproducible packets)

**Blockers**

- Tamper evidence for verifier devices: No tamper-evident enclosure has been designed for AI verifier hardware at retrofit scale. (hardware trust) [7]
- Tamper evidence for verifier devices: Battery-backed designs add bulk, limit operating temperature (+10 °C to +35 °C for the IBM 4765) and complicate transport. (performance & compatibility) [2]
- Tamper evidence for verifier devices: Active monitoring needs power, and visual inspection of large enclosures faces access limits. (access & governance) [6]
- Tamper evidence for verifier devices: No evaluation has been published in the AI verification setting. (adversarial validation) [7]
- Whole-workload recomputation (reproducible packets): Workloads are not reproducible by default, and achieving reproducibility may cost performance. (performance & compatibility; waits on Deterministic and bit-exact inference) [11]
- Whole-workload recomputation (reproducible packets): Network packets are not individually reproducible by default; making them so may need considerable software, firmware and hardware work. Amodo rates this 'not on track'. (performance & compatibility) [14]
- Whole-workload recomputation (reproducible packets): All traffic must reach the recomputation server via network taps, and the server's integrity is critical. (hardware trust; waits on Network taps and certifiers) [11][14]
- Whole-workload recomputation (reproducible packets): Recomputing training steps needs checkpoints: writing one at every step would cost more than 100% overhead, so Amodo's design needs a spare data-parallel replica that tracks the weights instead. (performance & compatibility) [12]
- Deterministic and bit-exact inference: Batch-invariant kernels cost throughput: in Thinking Machines' Qwen3-8B test, an improved deterministic build took 42 s against 26 s for vLLM's default, and SGLang reports an average 34.35% slowdown on its FlashInfer and FlashAttention 3 backends. (performance & compatibility) [18][20]
- Deterministic and bit-exact inference: Coverage is incomplete: the bit-exact emulator targets dense blocks on NVIDIA GPUs and excludes mixture-of-experts inference and training, and vLLM's batch-invariant mode is in beta, with open work on AMD hardware and speculative decoding. (performance & compatibility) [17][21][27]
- Deterministic and bit-exact inference: Amodo's status page for the AI 2040 verification plan rates a reproducible inference stack for that plan as 'not started'. (performance & compatibility) [14]
- Deterministic and bit-exact inference: Exact replay requires the prover to disclose weights, software versions, parallelism and batch sizes to whoever recomputes. (privacy & leakage) [7][17]


## What the verifier sees

- Model weights: shown by none; depends on the design for Whole-workload recomputation (reproducible packets) and Deterministic and bit-exact inference; hidden by none; not involved in Tamper evidence for verifier devices; unspecified for none.
- Inputs and outputs: shown by none; depends on the design for Whole-workload recomputation (reproducible packets) and Deterministic and bit-exact inference; hidden by none; not involved in Tamper evidence for verifier devices; unspecified for none.
- Training data: shown by none; depends on the design for Whole-workload recomputation (reproducible packets); hidden by none; not involved in Tamper evidence for verifier devices and Deterministic and bit-exact inference; unspecified for none.

## Implementations

- Tamper evidence for verifier devices: [AI 2040 inference-only verification stack](https://trustbutveri.fyi/implementations/ai-2040-inference-only-verification-plan/) (R1, proposed architecture)
- Whole-workload recomputation (reproducible packets): [AI 2040 inference-only verification stack](https://trustbutveri.fyi/implementations/ai-2040-inference-only-verification-plan/) (R1, proposed architecture)
- Deterministic and bit-exact inference: [Batch-invariant inference kernels (Thinking Machines)](https://trustbutveri.fyi/implementations/batch-invariant-inference-kernels/) (R2, open-source project); [Verde and RepOps (Gensyn)](https://trustbutveri.fyi/implementations/gensyn-verde-repops/) (R3, product); [Low-trust AI compute verification system overview](https://trustbutveri.fyi/implementations/low-trust-compute-verification-system-overview/) (R1, proposed architecture)

## Sources

1. Anti-Tamper Radio: System-Level Tamper Detection for Computing Systems, P. Staat et al. (2022). https://ieeexplore.ieee.org/document/9833631/
2. Secure Physical Enclosures from Covers with Tamper-Resistance, V. Immler et al. (2019). https://tches.iacr.org/index.php/TCHES/article/view/7334
3. ImpedanceVerif: On-Chip Impedance Sensing for System-Level Tampering Detection, T. Mosavirik et al. (2023). https://eprint.iacr.org/2022/946
4. IBM 4765 Cryptographic Coprocessor Security Module: Security Policy, IBM Corporation (2012). https://csrc.nist.gov/csrc/media/projects/cryptographic-module-validation-program/documents/security-policies/140sp1505.pdf
5. PHYSEC SEAL: Change detection for maximum safety, PHYSEC GmbH (2026). https://www.physec.de/en/solutions/physec-seal/
6. Tamper-Indicating Enclosures, A Current Survey, H. A. Smartt & Z. N. Gastelum (2015). https://www.osti.gov/servlets/purl/1256541
7. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). https://intelligence.org/wp-content/uploads/2026/06/A-system-overview-for-near-term-low-trust-AI-compute-verification.pdf
8. Physical Security and Tamper-Indicating Devices, R. G. Johnston & A. R. E. Garcia (1996). https://www.osti.gov/servlets/purl/459707
9. Tamper Detection for Safeguards and Treaty Monitoring: Fantasies, Realities, and Potentials, R. G. Johnston (2001). https://www.nonproliferation.org/wp-content/uploads/npr/81john.pdf
10. Anti-Tamper Radio Meets Reconfigurable Intelligent Surface for System-Level Tamper Detection, M. S. Tabar et al. (2025). https://arxiv.org/abs/2503.14279
11. Verification Plan, R. Dean (2026). https://ai-2040.com/supplements/verification-plan
12. Example Schemes for Verifying High-Stakes AI Agreements, Amodo Design (2026). https://amododesign.com/notes/2026-06-23-verification-algorithms/
13. Scaling Recomputation Inference Verification, Amodo Design (2026). https://amododesign.com/notes/2026-09-02-scaling-recomputation-inference-verification/
14. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). https://amododesign.com/ai-verification/plan-a-sitrep/
15. Get Involved in Verification, AI Futures Project (2026). https://ai-2040.com/supplements/verification-plan/get-involved
16. Proof-of-Learning is Currently More Broken Than You Think, C. Fang et al. (2023). https://arxiv.org/abs/2208.03567
17. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). https://arxiv.org/abs/2606.00279
18. Defeating Nondeterminism in LLM Inference, H. He & Thinking Machines Lab (2025). https://thinkingmachines.ai/blog/defeating-nondeterminism-in-llm-inference/
19. Hawkeye: Reproducing GPU-Level Non-Determinism, E. Badash et al. (2026). https://proceedings.mlsys.org/paper_files/paper/2026/hash/e217c271a57c365a246b0ad39e668ba8-Abstract-Conference.html
20. Towards Deterministic Inference in SGLang and Reproducible RL Training, The SGLang Team (2025). https://www.lmsys.org/blog/2025-09-22-sglang-deterministic/
21. Batch Invariance (vLLM documentation), vLLM project (2026). https://github.com/vllm-project/vllm/blob/main/docs/features/batch_invariance.md
22. gensyn-ai/ree: Gensyn Reproducible Execution Environment (GitHub repository), Gensyn (2026). https://github.com/gensyn-ai/ree
23. EigenCloud Brings Verifiable AI to Mass Market with EigenAI and EigenCompute Launches, EigenCloud (2025). https://www.eigenlabs.org/blog/eigencloud-brings-verifiable-ai-to-mass-market-with-eigenai-and-eigencompute-launches/
24. Building Delphi: Pricing, Settlement, and Agentic Trading, D. Jedamski (2026). https://www.gensyn.ai/blog/building-delphi-pricing-settlement-and-agentic-trading
25. Reproducible Execution Environment (REE) (Gensyn documentation), Gensyn (2026). https://docs.gensyn.ai/tech
26. What is Delphi? (Delphi documentation), Gensyn (2026). https://docs.delphi.fyi/
27. [Feature]: Batch Invariant Feature and Performance Optimization (vLLM issue #27433), vLLM project contributors (2025). https://github.com/vllm-project/vllm/issues/27433