# AI verification proposal

A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-08. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0018,M-0009,M-0017&coop=partial

How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's readiness and open flaws. Readiness levels R0 to R4 describe one record's public evidence for its assessed use and are never combined. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and flaws) and https://trustbutveri.fyi/about/readiness/ (readiness levels).

## Filters

Filters apply to mechanisms only and describe the setting the proposal is for.

- **Prover cooperation: Partial at most.** "Partial at most" removes mechanisms that need the prover's active participation. "Not required" keeps only those that work without it. Required: the prover takes part, for example by logging requests, producing proofs or opening records. Partial: some access, such as installing a device. Not required: works from outside, such as satellite imagery.

6 of 25 mechanisms on the map pass these filters.

## Overview

One row per mechanism, read from its record. Open flaws: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees.

| Mechanism | Readiness | Prover | Attack testing | Hardware | Open flaws | Weights | Inputs and outputs | Training data |
| --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Chip location verification (excluded by the filters) | R1 | Adversarial | Analysis | Existing features | 0 / 4 / 0 | not involved | not involved | not involved |
| Hardware-enabled guarantees (flexHEG) and guarantee processors (excluded by the filters) | R1 | Adversarial | Analysis | New chip design | 0 / 6 / 0 | hidden | hidden | hidden |
| Tamper evidence for verifier devices | R2 | Adversarial | Analysis | Retrofit device | 0 / 3 / 0 | not involved | not involved | not involved |

## Claims

No claims chosen.

## Mechanisms

### Chip location verification

Timing a chip's signed replies to trusted servers at known places, so that the speed of light bounds how far away the chip can be. ([Chip location verification](https://trustbutveri.fyi/mechanisms/chip-location-verification/))

- Assessment: mechanism family.
- Readiness: R1 Proposed, assessed for bounding how far a chip is from trusted landmark servers when checked.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: existing features. Prover cooperation: required. Attack testing: analysis. Category: Compute accounting & provenance.
- What the verifier sees: model weights not involved; inputs and outputs not involved; training data not involved. Times signed replies from chips; it does not handle model data.
- Filter conflict: Prover cooperation is required; the filter allows partial at most.

### Hardware-enabled guarantees (flexHEG) and guarantee processors

Proposed chip add-ons, a guarantee processor inside a tamper-protected enclosure, that would check and enforce agreed rules on how AI accelerators are used. ([Hardware-enabled guarantees (flexHEG) and guarantee processors](https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/))

- Assessment: mechanism family.
- Readiness: R1 Proposed, assessed for checking and enforcing training-compute limits on chips, against adversaries up to states.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: new chip design. Prover cooperation: required. Attack testing: analysis. Category: On-chip & hardware-enabled.
- What the verifier sees: model weights hidden; inputs and outputs hidden; training data hidden. The guarantee processor sees the chip's traffic inside a sealed enclosure and reports only whether rules were kept.
- Filter conflict: Prover cooperation is required; the filter allows partial at most.

### Tamper evidence for verifier devices

Enclosures, seals and sensors that make physical interference with verification hardware either visible or self-defeating. ([Tamper evidence for verifier devices](https://trustbutveri.fyi/mechanisms/tamper-evidence-for-verifier-devices/))

- Assessment: mechanism family.
- Readiness: R2 Demonstrated, assessed for detecting probing of proposed verifier hardware, using server and electronics prototypes as evidence.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: retrofit device. Prover cooperation: partial. Attack testing: analysis. Category: Off-chip devices & sensors.
- What the verifier sees: model weights not involved; inputs and outputs not involved; training data not involved. Protects verifier devices; it does not handle model data.


## Properties

**Built for an adversarial prover**

- Tamper evidence for verifier devices

Not counted as properties, because the filters exclude them: Chip location verification and Hardware-enabled guarantees (flexHEG) and guarantee processors.


## Attack testing

Published attempts to break a system, including those that found failures. Testing history does not establish that open flaws are resolved.

**Testing history**

- Chip location verification: Analysis (excluded by filters)
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Analysis (excluded by filters)
- Tamper evidence for verifier devices: Analysis


## Limits

**Excluded by the filters**

- Chip location verification: Prover cooperation is required; the filter allows partial at most.
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Prover cooperation is required; the filter allows partial at most.

**Open significant flaws**

- Extracting a chip's key lets another device answer for it (theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/#flaw-1) [1][6]. Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM.
- Added delay can shift an estimated position (demonstrated attack, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/#flaw-2) [1][4]. Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location.
- Faster-than-assumed network paths (theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/#flaw-3) [1][4]. Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often.
- Compromised landmarks can falsify measurements (theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/#flaw-4) [1][4][5]. A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators.
- State attackers can likely defeat current secure enclosures (theoretical argument, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-1) [9][11]. The flexHEG authors write that "nation-state attackers can likely compromise the best current secure enclosures", and that the marginal cost of circumvention per device is hard to estimate. RAND similarly judges that anti-tamper measures "would not be insurmountable for a determined and well-resourced adversary", although they raise costs and can reveal tampering.
- Firmware-only retrofits rely on Secure Boot, which fault injection can bypass (theoretical argument, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-2) [9]. Part II notes that the most common attack on Secure Boot replaces the firmware and applies a voltage glitch while the signature is being checked. It also notes that sophisticated actors may use microprobing or laser voltage probing to read key registers.
- Many important rules cannot be checked on-chip (theoretical argument, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-3) [8][10]. Malicious intent "is not a technical property observable on-chip", and misuse depends on what is done with a computation's results. A guarantee processor cannot easily tell whether a network is the whole system or one expert in a mixture-of-experts system. Part III judges that a fully local ruleset "may not be entirely feasible" for the same reason.
- FLOP accounting can be laundered through external data (theoretical argument, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-4) [9]. Results of earlier or parallel workloads could be hidden in the "external data" fed to a device, which would falsify the total FLOP count unless the inputs are explained or time delays are imposed.
- Supply-chain diversion and hidden backdoors (open question, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-5) [9][10]. Components could be diverted before a guarantee processor is added, and backdoors could be introduced during design or manufacturing. Open-source designs and physical scans of randomly selected chips are proposed as countermeasures. Part III proposes international oversight of production and extensive testing of a random sample of finished devices.

  Related mechanism: Chip registries and manufacturing records (R1, not in the proposal). Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors.
- Coverage stops at flexHEG-equipped chips (open question, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-6) [8][10]. Motivated actors will always be able to use some compute that is not flexHEG-equipped. Recalling existing consumer GPUs would likely be impractical, and reaching perfect coverage, or conclusively proving that no secret government data centres exist, would be "practically quite difficult".

  Related mechanism: Chip registries and manufacturing records (R1, not in the proposal). Accounts for which chips exist and who holds them.

  Related mechanism: Remote detection of data centres (R1, not in the proposal). Looks for undeclared facilities that hold other chips.
- Seals are often defeated with simple methods (demonstrated attack, in Tamper evidence for verifier devices; https://trustbutveri.fyi/mechanisms/tamper-evidence-for-verifier-devices/#flaw-1) [20][21]. Mechanism-class evidence. Published defeats of general security seals. They warn about proposed verifier-device seals, but do not demonstrate defeat of an AI verification enclosure or sensor. In 1996 a Los Alamos vulnerability assessment defeated all 94 security seals it examined, with 132 defeats in total, using rapid, inexpensive, low-tech methods. It found that seal cost did not predict security. In 2001 Johnston reported that high-tech seals are often easier to defeat than low-tech ones.
- Security depends on inspection protocols (theoretical argument, in Tamper evidence for verifier devices; https://trustbutveri.fyi/mechanisms/tamper-evidence-for-verifier-devices/#flaw-2) [18][21]. Mechanism-class evidence. An inspection and protocol requirement drawn from safeguards and enclosure studies, not a reported break of a deployed AI verifier. Johnston argues that a seal is no better than the protocols for using it, and that inspectors are usually given little useful information on how to detect tampering. The Sandia survey notes that larger enclosures are hard to inspect fully and that sensor data must be authenticated.
- Attack classes outside published models (open question, in Tamper evidence for verifier devices; https://trustbutveri.fyi/mechanisms/tamper-evidence-for-verifier-devices/#flaw-3) [13][14][22]. Mechanism-class evidence. The radio compensation result is emulated using measured channel data under a known-reference attacker model. It is not a physical bypass demonstration against an AI verifier enclosure. The authors of the batteryless cover say they cannot assess chemical-solvent attacks, which exceed their expertise, and deem cover removal impractical. Anti-Tamper Radio's reference can drift as the environment or measurement system ages; the authors suggest gradually renewing the reference. A 2025 follow-up by some of the same authors shows, by emulation on measured channel data, that an attacker who knows the reference channel and the needle's effect on it could inject a signal that cancels the change caused by a needle insertion. It proposes a reconfigurable intelligent surface that randomizes the channel as a countermeasure.

**Not yet demonstrated**

- Chip location verification: R1 Proposed, assessed for bounding how far a chip is from trusted landmark servers when checked
- Hardware-enabled guarantees (flexHEG) and guarantee processors: R1 Proposed, assessed for checking and enforcing training-compute limits on chips, against adversaries up to states

**Need new chip designs**

- Hardware-enabled guarantees (flexHEG) and guarantee processors


## Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open flaw or a dependency. Pointers, not recommendations: each brings its own readiness level and flaws, and none is claimed to close a flaw.

- **Remote detection of data centres** (R1 Proposed, assessed for finding undeclared data centres above an agreed compute threshold)
  - Bears on the open significant flaw "Coverage stops at flexHEG-equipped chips" in Hardware-enabled guarantees (flexHEG) and guarantee processors. Looks for undeclared facilities that hold other chips.
- **Chip registries and manufacturing records** (R1 Proposed, assessed for a checkable record of which chips were made and who declared owning them). Excluded by the filters: prover cooperation required
  - Bears on the open significant flaw "Supply-chain diversion and hidden backdoors" in Hardware-enabled guarantees (flexHEG) and guarantee processors. Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors.
  - Bears on the open significant flaw "Coverage stops at flexHEG-equipped chips" in Hardware-enabled guarantees (flexHEG) and guarantee processors. Accounts for which chips exist and who holds them.
  - Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it: Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities.
- **TEE remote attestation for AI workloads** (R3 In production, assessed for showing which software ran to a party that distrusts the operator holding the hardware). Excluded by the filters: prover cooperation required
  - Chip location verification depends on it.
  - Hardware-enabled guarantees (flexHEG) and guarantee processors depends on it.


## Dependencies

**Missing prerequisites**

- TEE remote attestation for AI workloads (R3 In production, assessed for showing which software ran to a party that distrusts the operator holding the hardware), needed by Chip location verification and Hardware-enabled guarantees (flexHEG) and guarantee processors
- Chip registries and manufacturing records (R1 Proposed, assessed for a checkable record of which chips were made and who declared owning them), needed by Hardware-enabled guarantees (flexHEG) and guarantee processors

**Shared foundations**

- TEE remote attestation for AI workloads, relied on by Chip location verification and Hardware-enabled guarantees (flexHEG) and guarantee processors

**Blockers**

- Chip location verification: No public code or reproducible end-to-end location results are available for the reported H100 prototype. (adversarial validation) [2][3]
- Chip location verification: Per-chip keys must be provisioned and protected against extraction; hardware-integrated, tamper-resistant versions still need R&D. (hardware trust) [1][6][23]
- Chip location verification: The time limit forces a trade-off: a limit at the speed of light in fibre can be beaten by faster links, while one at the vacuum speed of light makes honest chips fail often. (protocol soundness) [1]
- Chip location verification: A trusted landmark network must be built and secured, and who should operate it, under what oversight, is unsettled. (access & governance) [1][4]
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Integrated flexHEG needs substantial help from the accelerator manufacturer, and the authors estimate 3.7–7.9 years, from when the manufacturer starts work, for such hardware to displace other accelerators in frontier development. (access & governance) [9]
- Hardware-enabled guarantees (flexHEG) and guarantee processors: State-level attackers who hold the hardware can likely compromise the best current secure enclosures. (hardware trust; waits on Tamper evidence for verifier devices) [9][11]
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Rival states would need to trust the design and manufacture of guarantee processors and enclosures, for example through open design, redundant processors from each side or oversight of production. (hardware trust) [8][10]
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Restricting future rule updates would need a formal language for rules, which the authors judge most likely infeasible for early flexHEG versions. (protocol soundness) [8]
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities. (coverage & hidden compute; waits on Chip registries and manufacturing records) [10]
- Tamper evidence for verifier devices: No tamper-evident enclosure has been designed for AI verifier hardware at retrofit scale. (hardware trust) [19]
- Tamper evidence for verifier devices: Battery-backed designs add bulk, limit operating temperature (+10 °C to +35 °C for the IBM 4765) and complicate transport. (performance & compatibility) [14]
- Tamper evidence for verifier devices: Active monitoring needs power, and visual inspection of large enclosures faces access limits. (access & governance) [18]
- Tamper evidence for verifier devices: No evaluation has been published in the AI verification setting. (adversarial validation) [19]


## What the verifier sees

- Model weights: shown by none; depends on the design for none; hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors; not involved in Chip location verification and Tamper evidence for verifier devices; unspecified for none.
- Inputs and outputs: shown by none; depends on the design for none; hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors; not involved in Chip location verification and Tamper evidence for verifier devices; unspecified for none.
- Training data: shown by none; depends on the design for none; hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors; not involved in Chip location verification and Tamper evidence for verifier devices; unspecified for none.

## Implementations

- Chip location verification: [Lucid sovereignty (location) certificates](https://trustbutveri.fyi/implementations/lucid-location-certificates/) (R1, standard)
- Hardware-enabled guarantees (flexHEG) and guarantee processors: none on the map
- Tamper evidence for verifier devices: [AI 2040 inference-only verification stack](https://trustbutveri.fyi/implementations/ai-2040-inference-only-verification-plan/) (R1, proposed architecture)

## Sources

1. Location Verification for AI Chips, A. Brass & O. Aarne (2024). https://www.iaps.ai/research/location-verification-for-ai-chips
2. Location Verification for AI Chips (issue brief), A. Brass (2025). https://static1.squarespace.com/static/64edf8e7f2b10d716b5ba0e1/t/6827b67275666f3757f134ea/1747433075281/Location+Verification+two-pager.pdf
3. Ping-based Location, Ulyssean (2025). https://ping-location.info/
4. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). https://www.iaps.ai/research/near-term-verification-methods-for-ai-chip-exports
5. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). https://github.com/Lucid-Computing/sovereignty-certificate-specification
6. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). https://arxiv.org/abs/2605.01930
7. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). https://www.cnas.org/publications/reports/secure-governable-chips
8. Flexible Hardware-Enabled Guarantees for AI Compute, J. Petrie et al. (2025). https://arxiv.org/abs/2506.15093
9. Technical Options for Flexible Hardware-Enabled Guarantees, J. Petrie & O. Aarne (2025). https://arxiv.org/abs/2506.03409
10. International Security Applications of Flexible Hardware-Enabled Guarantees, O. Aarne & J. Petrie (2025). https://arxiv.org/abs/2506.15100
11. Hardware-Enabled Governance Mechanisms: Developing Technical Solutions to Exempt Items Otherwise Classified Under Export Control Classification Numbers 3A090 and 4A090, G. Kulp et al. (2024). https://www.rand.org/pubs/working_papers/WRA3056-1.html
12. Hardware-Enabled Mechanisms for Verifying Responsible AI Development, A. O'Gara et al. (2025). https://arxiv.org/abs/2505.03742
13. Anti-Tamper Radio: System-Level Tamper Detection for Computing Systems, P. Staat et al. (2022). https://ieeexplore.ieee.org/document/9833631/
14. Secure Physical Enclosures from Covers with Tamper-Resistance, V. Immler et al. (2019). https://tches.iacr.org/index.php/TCHES/article/view/7334
15. ImpedanceVerif: On-Chip Impedance Sensing for System-Level Tampering Detection, T. Mosavirik et al. (2023). https://eprint.iacr.org/2022/946
16. IBM 4765 Cryptographic Coprocessor Security Module: Security Policy, IBM Corporation (2012). https://csrc.nist.gov/csrc/media/projects/cryptographic-module-validation-program/documents/security-policies/140sp1505.pdf
17. PHYSEC SEAL: Change detection for maximum safety, PHYSEC GmbH (2026). https://www.physec.de/en/solutions/physec-seal/
18. Tamper-Indicating Enclosures, A Current Survey, H. A. Smartt & Z. N. Gastelum (2015). https://www.osti.gov/servlets/purl/1256541
19. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). https://intelligence.org/wp-content/uploads/2026/06/A-system-overview-for-near-term-low-trust-AI-compute-verification.pdf
20. Physical Security and Tamper-Indicating Devices, R. G. Johnston & A. R. E. Garcia (1996). https://www.osti.gov/servlets/purl/459707
21. Tamper Detection for Safeguards and Treaty Monitoring: Fantasies, Realities, and Potentials, R. G. Johnston (2001). https://www.nonproliferation.org/wp-content/uploads/npr/81john.pdf
22. Anti-Tamper Radio Meets Reconfigurable Intelligent Surface for System-Level Tamper Detection, M. S. Tabar et al. (2025). https://arxiv.org/abs/2503.14279
23. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). https://arxiv.org/abs/2604.04712