# AI verification proposal

A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-09. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0024,M-0018,M-0014&hide=weights,training

How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's development status, security evidence and findings. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and findings) and https://trustbutveri.fyi/about/readiness/ (development status).

## Filters

Filters apply to mechanisms only and describe the setting the proposal is for.

- **Keep hidden from the verifier: model weights, training data.** Removes mechanisms that show the asset to the verifier. Conditional or unspecified exposure stays with a note and needs checking against the privacy requirement. Model weights: the checked model's parameters. Inputs and outputs: the requests a deployed model serves and its responses. Training data: what a model was trained on. Each mechanism's exposure is the editors' reading of its record: shown, depends on the design (kept, with a note), hidden, not involved, or unspecified for a selected implementation. Code and configuration are not covered yet.

24 of 25 mechanisms on the map pass these filters.

## Overview

One row per mechanism, read from its record. Open failures: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees. Findings are grouped as known failures, scope limitations and open questions. Only known failures count as failures. Counts are an inventory of published findings, not a risk score.

| Mechanism | Development | Security evidence | Prover | Attack testing | Hardware | Open failures | Weights | Inputs and outputs | Training data |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Bounding unexplained information in outputs | Research demonstration | Published attack testing | Adversarial | Independent red-team | Retrofit device | 0 / 1 / 0 | depends | depends | not involved |
| Chip location verification | Proposed | Published security analysis | Adversarial | Analysis | Existing features | 0 / 4 / 0 | not involved | not involved | not involved |
| Bandwidth limits and compartmentalization | Research demonstration | Published security analysis | Adversarial | Analysis | Retrofit device | 0 / 2 / 0 | not involved | not involved | not involved |

## Claims

No claims chosen.

## Mechanisms

### Bounding unexplained information in outputs

Limits the hidden information a facility's outputs can carry by measuring how much of those outputs the declared computation fails to predict. ([Bounding unexplained information in outputs](https://trustbutveri.fyi/mechanisms/bounding-unexplained-information/))

- Assessment: mechanism family.
- Development: Research demonstration (legacy code R2), assessed for bounding how much hidden information can leave in checked inference outputs.
- Security evidence: Published attack testing. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: retrofit device. Prover cooperation: required. Attack testing: independent red-team. Category: Isolation & system architectures.
- What the verifier sees: model weights depends; inputs and outputs depends; training data not involved. Depends on where recomputation runs: in a sealed enclosure, or with zero-knowledge proofs, the verifier need not see the weights or the traffic.
- Filter note: May show model weights, depending on the design. Depends on where recomputation runs: in a sealed enclosure, or with zero-knowledge proofs, the verifier need not see the weights or the traffic.

### Chip location verification

Timing a chip's signed replies to trusted servers at known places, so that the speed of light bounds how far away the chip can be. ([Chip location verification](https://trustbutveri.fyi/mechanisms/chip-location-verification/))

- Assessment: mechanism family.
- Development: Proposed (legacy code R1), assessed for bounding how far a chip is from trusted landmark servers when checked.
- Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: existing features. Prover cooperation: required. Attack testing: analysis. Category: Compute accounting & provenance.
- What the verifier sees: model weights not involved; inputs and outputs not involved; training data not involved. Times signed replies from chips; it does not handle model data.

### Bandwidth limits and compartmentalization

Capping or removing network links between groups of AI chips, so each group can serve models but large training runs across groups become far slower. ([Bandwidth limits and compartmentalization](https://trustbutveri.fyi/mechanisms/bandwidth-limits-and-compartmentalization/))

- Assessment: mechanism family.
- Development: Research demonstration (legacy code R2), assessed for monitoring inter-node traffic with operator-run software on four GPUs.
- Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: retrofit device. Prover cooperation: required. Attack testing: analysis. Category: Isolation & system architectures.
- What the verifier sees: model weights not involved; inputs and outputs not involved; training data not involved. Caps traffic between groups of chips; it does not read the traffic's content.


## Properties

**Built for an adversarial prover**

- Bounding unexplained information in outputs
- Chip location verification
- Bandwidth limits and compartmentalization

**No new hardware needed**

- Chip location verification


## Attack testing

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

**Testing history**

- Bounding unexplained information in outputs: Independent red-team
- Chip location verification: Analysis
- Bandwidth limits and compartmentalization: Analysis


## Limits

**Open significant failures**

- Prompt-controlled entropy inflation widens the covert channel (known failure, demonstrated attack, in Bounding unexplained information in outputs; https://trustbutveri.fyi/mechanisms/bounding-unexplained-information/evidence/flaws/1/) [2][3]. Gumbel-based inference verification tolerates token choices that honest GPU nondeterminism could produce, and the size of that tolerated set grows with the model's output entropy. Kezins, an independent researcher, showed that an adversary who controls the prompt distribution can raise output entropy and roughly double the bits leaked per token. Across six models of 1 to 32 billion parameters, this cut the slowdown from 146–254 times under benign prompts to 60–118 times. Kezins argues that architectures built on the same unexplained-information bound inherit this attack surface, and recommends calibrating tolerances against local token entropy rather than benign traffic.

  Related mechanism: Deterministic and bit-exact inference (R3, not in the proposal). Bit-exact replay would remove the tolerance for numerical noise that sets the size of this channel. The record notes that it needs full hardware and software metadata.
- Extracting a chip's key lets another device answer for it (known failure, theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/evidence/flaws/1/) [6][11]. Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM.
- Added delay can shift an estimated position (known failure, demonstrated attack, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/evidence/flaws/2/) [6][9]. Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location.
- Faster-than-assumed network paths (known failure, theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/evidence/flaws/3/) [6][9]. Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often.
- Compromised landmarks can falsify measurements (known failure, theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/evidence/flaws/4/) [6][9][10]. A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators.
- Operator control of pod routing collapses the bound (known failure, theoretical argument, in Bandwidth limits and compartmentalization; https://trustbutveri.fyi/mechanisms/bandwidth-limits-and-compartmentalization/evidence/flaws/2/) [14]. Lucid's analysis finds that if the operator can freely assign pods to routers, it could dedicate a whole cell of 100 or more pods to one pipeline stage. The bound then falls to about 90–220x uncompressed and as low as about 25x with compression. The proposed mitigation, auditor-controlled random assignment that is periodically re-randomized, has not been implemented.
- Parallel scale-up switches are hard enforcement points (known failure, theoretical argument, in Bandwidth limits and compartmentalization; https://trustbutveri.fyi/mechanisms/bandwidth-limits-and-compartmentalization/evidence/flaws/5/) [16]. In GB200 topologies, GPUs reach GPUs in other nodes through NVSwitches without a NIC on the path. Amodo notes that limits are hard to enforce there because many switches work in parallel, so compromising one or two would bypass the limit.

**Scope limitations**

- Information the declared computation explains is not bounded (scope limitation, theoretical argument, in Bounding unexplained information in outputs; https://trustbutveri.fyi/mechanisms/bounding-unexplained-information/evidence/flaws/2/) [1][4]. The bound limits unexplained bits only. Outputs that the declared computation fully explains can still carry valuable information: a compression study notes that an adversary with inference access can extract more proprietary information per bit than naive transmission allows.
- Channels other than checked outputs are outside the bound (scope limitation, theoretical argument, in Bounding unexplained information in outputs; https://trustbutveri.fyi/mechanisms/bounding-unexplained-information/evidence/flaws/3/) [2][5]. The inference-verification scheme treats side channels as out of scope. A low-trust system design argues that suppressing physical covert bandwidth below kilobits per second is much more achievable than aiming for zero, and that a malicious device can leak one bit of information by deliberately outputting a wrong result.

  Related mechanism: Side-channel suppression for isolated facilities (R1, not in the proposal). Physical side channels need separate suppression, which is this mechanism's purpose.
- Undeclared local storage raises per-pod capacity (scope limitation, theoretical argument, in Bandwidth limits and compartmentalization; https://trustbutveri.fyi/mechanisms/bandwidth-limits-and-compartmentalization/evidence/flaws/3/) [14]. More memory or storage per pod helps an adversary. Lucid requires per-pod storage to be declared, capped and physically inspected.
- Training within one pod is not covered (scope limitation, open question, in Bandwidth limits and compartmentalization; https://trustbutveri.fyi/mechanisms/bandwidth-limits-and-compartmentalization/evidence/flaws/4/) [14]. Lucid's bounds concern pre-training models larger than the pods are sized for. Training models that fit in one pod, fine-tuning and reinforcement-learning post-training within one pod are outside the modelled threat.

**Open questions**

- The facility-level design is untested (open question, open question, in Bounding unexplained information in outputs; https://trustbutveri.fyi/mechanisms/bounding-unexplained-information/evidence/flaws/4/) [1]. The compute-verification architecture is described with protocol details, potential attacks and prototyping plans, but no prototype results have been published.
- Low-communication training reduces the bandwidth training needs (open question, theoretical argument, in Bandwidth limits and compartmentalization; https://trustbutveri.fyi/mechanisms/bandwidth-limits-and-compartmentalization/evidence/flaws/1/) [14][17][18]. DiLoCo matched fully synchronous training on 8 workers while communicating 500 times less. Rahman writes that this family of methods theoretically allows large-scale training with less than 100 Mbps. Lucid includes these methods in its bounds, but notes that extreme activation compression, architectures with unusually small inter-layer widths, or modular paradigms could erode the margin.

**Not yet demonstrated**

- Chip location verification: Proposed (legacy code R1), assessed for bounding how far a chip is from trusted landmark servers when checked


## Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open failure or a dependency. Pointers, not recommendations: each brings its own readiness level and findings, and none is claimed to close a failure.

- **Deterministic and bit-exact inference** (Operational use (legacy code R3), assessed for reproducing open-model inference from receipts in Gensyn's information-market service)
  - Bears on the open significant failure "Prompt-controlled entropy inflation widens the covert channel" in Bounding unexplained information in outputs. Bit-exact replay would remove the tolerance for numerical noise that sets the size of this channel. The record notes that it needs full hardware and software metadata.
  - Bounding unexplained information in outputs waits on it: Tolerance for numerical nondeterminism sets the size of the residual channel; bit-exact replay would remove it but needs full hardware and software metadata.
- **Tamper evidence for verifier devices** (Research demonstration (legacy code R2), assessed for detecting probing of proposed verifier hardware, using server and electronics prototypes as evidence)
  - Bandwidth limits and compartmentalization waits on it: Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU.
- **Network taps and certifiers** (Proposed (legacy code R1), assessed for committing a complete record of cluster traffic, so declared inference can be checked)
  - Bandwidth limits and compartmentalization waits on it: The verifier must know that all traffic leaving a pod crosses the capped, monitored links.
  - Bounding unexplained information in outputs depends on it.
- **Side-channel suppression for isolated facilities** (Proposed (legacy code R1), assessed for bounding physical covert channels out of a verified enclosure)
  - Bounding unexplained information in outputs waits on it: Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target.
- **Sampled inference recomputation** (Operational use (legacy code R3), assessed for checking untrusted workers' activations against the declared model, prompt and precision)
  - Bounding unexplained information in outputs depends on it.
- **TEE remote attestation for AI workloads** (Operational use (legacy code R3), assessed for showing which software ran to a party that distrusts the operator holding the hardware)
  - Chip location verification depends on it.


## Dependencies

**Missing prerequisites**

- Sampled inference recomputation (Operational use (legacy code R3), assessed for checking untrusted workers' activations against the declared model, prompt and precision), needed by Bounding unexplained information in outputs
- Side-channel suppression for isolated facilities (Proposed (legacy code R1), assessed for bounding physical covert channels out of a verified enclosure), needed by Bounding unexplained information in outputs
- Network taps and certifiers (Proposed (legacy code R1), assessed for committing a complete record of cluster traffic, so declared inference can be checked), needed by Bounding unexplained information in outputs
- TEE remote attestation for AI workloads (Operational use (legacy code R3), assessed for showing which software ran to a party that distrusts the operator holding the hardware), needed by Chip location verification
- Tamper evidence for verifier devices (Research demonstration (legacy code R2), assessed for detecting probing of proposed verifier hardware, using server and electronics prototypes as evidence), needed by Bandwidth limits and compartmentalization

**Shared foundations**

- Network taps and certifiers, relied on by Bounding unexplained information in outputs and Bandwidth limits and compartmentalization

**Blockers**

- Bounding unexplained information in outputs: The prover's compute must be isolated so that all traffic passes through the verifier's interlock; any unmonitored path voids the bound. (coverage & hidden compute; waits on Bandwidth limits and compartmentalization) [1]
- Bounding unexplained information in outputs: Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target. (coverage & hidden compute; waits on Side-channel suppression for isolated facilities) [2][5]
- Bounding unexplained information in outputs: Tolerance for numerical nondeterminism sets the size of the residual channel; bit-exact replay would remove it but needs full hardware and software metadata. (protocol soundness; waits on Deterministic and bit-exact inference) [3][5]
- Bounding unexplained information in outputs: Recomputation over confidential weights and inputs needs a protected setting: prover recomputation in a verifier-controlled enclosure, verifier recomputation in a prover-controlled enclosure, or zero-knowledge proofs. (privacy & leakage) [1]
- Bounding unexplained information in outputs: No prototype of the facility-level architecture exists to red-team. (adversarial validation) [1]
- Chip location verification: No public code or reproducible end-to-end location results are available for the reported H100 prototype. (adversarial validation) [7][8]
- Chip location verification: Per-chip keys must be provisioned and protected against extraction; hardware-integrated, tamper-resistant versions still need R&D. (hardware trust) [6][11][19]
- Chip location verification: The time limit forces a trade-off: a limit at the speed of light in fibre can be beaten by faster links, while one at the vacuum speed of light makes honest chips fail often. (protocol soundness) [6]
- Chip location verification: A trusted landmark network must be built and secured, and who should operate it, under what oversight, is unsettled. (access & governance) [6][9]
- Bandwidth limits and compartmentalization: No cap that a verifier can check has been implemented or red-teamed. (adversarial validation) [14]
- Bandwidth limits and compartmentalization: The verifier must know that all traffic leaving a pod crosses the capped, monitored links. (coverage & hidden compute; waits on Network taps and certifiers) [5]
- Bandwidth limits and compartmentalization: Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU. (hardware trust; waits on Tamper evidence for verifier devices) [14][16]
- Bandwidth limits and compartmentalization: Advances in low-communication training could shrink the margin that the cap enforces. (capacity bounds) [14][17][18]


## What the verifier sees

- Model weights: shown by none; depends on the design for Bounding unexplained information in outputs; hidden by none; not involved in Chip location verification and Bandwidth limits and compartmentalization; unspecified for none.
- Inputs and outputs: shown by none; depends on the design for Bounding unexplained information in outputs; hidden by none; not involved in Chip location verification and Bandwidth limits and compartmentalization; unspecified for none.
- Training data: shown by none; depends on the design for none; hidden by none; not involved in Bounding unexplained information in outputs, Chip location verification and Bandwidth limits and compartmentalization; unspecified for none.

## Implementations

- Bounding unexplained information in outputs: none on the map
- Chip location verification: [Lucid sovereignty (location) certificates](https://trustbutveri.fyi/implementations/lucid-location-certificates/) (R1, standard)
- Bandwidth limits and compartmentalization: [AI 2040 inference-only verification stack](https://trustbutveri.fyi/implementations/ai-2040-inference-only-verification-plan/) (R1, proposed architecture); [RAND secure inference data center (SIDC) design](https://trustbutveri.fyi/implementations/rand-secure-inference-data-centers/) (R1, proposed architecture)

## Sources

1. Verifying AI Compute by Bounding Unexplained Information Exfiltration, J. Petrie & Y. Mühlhäuser (2026). https://openreview.net/forum?id=qtgG5HZSsk
2. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). https://arxiv.org/abs/2511.02620
3. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). https://arxiv.org/abs/2608.23375
4. Haiku to Opus in Just 10 bits: LLMs Unlock Large Compression Gains, R. Rinberg et al. (2026). https://arxiv.org/abs/2604.02343
5. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). https://intelligence.org/wp-content/uploads/2026/06/A-system-overview-for-near-term-low-trust-AI-compute-verification.pdf
6. Location Verification for AI Chips, A. Brass & O. Aarne (2024). https://www.iaps.ai/research/location-verification-for-ai-chips
7. Location Verification for AI Chips (issue brief), A. Brass (2025). https://static1.squarespace.com/static/64edf8e7f2b10d716b5ba0e1/t/6827b67275666f3757f134ea/1747433075281/Location+Verification+two-pager.pdf
8. Ping-based Location, Ulyssean (2025). https://ping-location.info/
9. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). https://www.iaps.ai/research/near-term-verification-methods-for-ai-chip-exports
10. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). https://github.com/Lucid-Computing/sovereignty-certificate-specification
11. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). https://arxiv.org/abs/2605.01930
12. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). https://www.cnas.org/publications/reports/secure-governable-chips
13. Verification Plan, R. Dean (2026). https://ai-2040.com/supplements/verification-plan
14. Traffic Shaping for Workload Classification, Lucid Computing (2026). https://lucidcomputing.substack.com/p/traffic-shaping-for-workload-classification
15. De-risking Interconnect Limits for AI Verification, A. Scher et al. (2026). https://techgov.intelligence.org/blog/de-risking-interconnect-limits-for-ai-verification
16. The Tray as a Bandwidth Boundary, Amodo Design (2026). https://amododesign.com/notes/2026-03-16-dpu-bandwidth-limiter/
17. DiLoCo: Distributed Low-Communication Training of Language Models, A. Douillard et al. (2024). https://arxiv.org/abs/2311.08105
18. Does Distributed Training Undermine Compute Governance?, R. Rahman (2026). https://arxiv.org/abs/2605.29359
19. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). https://arxiv.org/abs/2604.04712