# AI verification proposal

A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-09. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0012,M-0010&implementations=M-0012:I-0007

How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's development status, security evidence and findings. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and findings) and https://trustbutveri.fyi/about/readiness/ (development status).

## Filters

Filters apply to mechanisms only and describe the setting the proposal is for.

None set. Every mechanism on the map was available.

## Overview

One row per mechanism, read from its record. Open failures: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees. Findings are grouped as known failures, scope limitations and open questions. Only known failures count as failures. Counts are an inventory of published findings, not a risk score.

| Mechanism | Development | Security evidence | Prover | Attack testing | Hardware | Open failures | Weights | Inputs and outputs | Training data |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Hardware-attested weight binding / Attestable Audits | Research demonstration | Published security analysis | Semi-trusted | Analysis | Existing features | 0 / 0 / 0 | unspecified | unspecified | unspecified |
| On-chip telemetry from timing, memory and performance counters | Research demonstration | Published attack testing | Semi-trusted | Red-teamed | Existing features | 0 / 2 / 0 | depends | depends | depends |

## Claims

No claims chosen.

## Mechanisms

### Hardware-attested weight binding

A research prototype that runs AI safety benchmarks inside a trusted execution environment and publishes hardware-signed records linking the model, the audit and the results. ([Hardware-attested weight binding](https://trustbutveri.fyi/mechanisms/model-identity-attestation/))

- Assessment: selected implementation [Attestable Audits](https://trustbutveri.fyi/implementations/attestable-audits/).
- Development: Research demonstration (legacy code R2), assessed for showing users that the model answering them is the audited one.
- Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: semi-trusted prover. Hardware: existing features. Prover cooperation: required. Attack testing: analysis. Category: On-chip & hardware-enabled.
- What the verifier sees: model weights unspecified; inputs and outputs unspecified; training data unspecified. This Explorer has no asset-specific exposure assessment for this implementation. Check its source and deployment assumptions.

### On-chip telemetry from timing, memory and performance counters

Uses on-chip measurements, such as task timings, whether data sits in chip memory, and performance counters, as evidence of what AI chips are running. ([On-chip telemetry from timing, memory and performance counters](https://trustbutveri.fyi/mechanisms/on-chip-telemetry/))

- Assessment: mechanism family.
- Development: Research demonstration (legacy code R2), assessed for workload evidence from GPU counters and timing, assuming authentic measurements.
- Security evidence: Published attack testing. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: semi-trusted prover. Hardware: existing features. Prover cooperation: partial. Attack testing: red-teamed. Category: On-chip & hardware-enabled.
- What the verifier sees: model weights depends; inputs and outputs depends; training data depends. Counters do not read weights or data, but richer counters can leak secrets through side channels.


## Properties

**No new hardware needed**

- Hardware-attested weight binding
- On-chip telemetry from timing, memory and performance counters


## Attack testing

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

**Testing history**

- Hardware-attested weight binding / Attestable Audits: Analysis
- On-chip telemetry from timing, memory and performance counters: Red-teamed


## Limits

**Open significant failures**

- Adversarially disguised fine-tuning partly evades classification (known failure, demonstrated attack, in On-chip telemetry from timing, memory and performance counters; https://trustbutveri.fyi/mechanisms/on-chip-telemetry/evidence/flaws/2/) [13]. Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware.
- Counters leak information about protected workloads (known failure, theoretical argument, in On-chip telemetry from timing, memory and performance counters; https://trustbutveri.fyi/mechanisms/on-chip-telemetry/evidence/flaws/4/) [2][10]. Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality.

**Family finding context**

- Context for Attestable Audits. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there. Underlying attestation can be forged or relayed (known failure, demonstrated attack, in Hardware-attested weight binding; https://trustbutveri.fyi/mechanisms/model-identity-attestation/evidence/flaws/1/) [3][4][5][6][7][8]. Inherited finding. Critical for weight binding against an operator with physical access to affected hardware, or with control of the hypervisor on an AMD SEV-SNP platform without AMD's fixes. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary. The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. Related finding: https://trustbutveri.fyi/mechanisms/tee-remote-attestation/evidence/flaws/1/.

  Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

  Related mechanism: Hardware-enabled guarantees (flexHEG) and guarantee processors (R1, not in the proposal). A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
- Context for Attestable Audits. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there. Launch-state attestation does not by itself cover weights loaded later (known failure, theoretical argument, in Hardware-attested weight binding; https://trustbutveri.fyi/mechanisms/model-identity-attestation/evidence/flaws/2/) [9][10]. Attestation measures launch state, and weights are read from disk after boot. A signature checked at load time does not stop a malicious hypervisor from altering the disk afterwards. Tinfoil reports mitigating this with dm-verity checks on every read. Unmeasured runtime configuration remains a general risk.
- Context for Attestable Audits. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there. For private models, a user can confirm consistency but not content (scope limitation, open question, in Hardware-attested weight binding; https://trustbutveri.fyi/mechanisms/model-identity-attestation/evidence/flaws/3/) [1][9]. When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy.

**Scope limitations**

- Relies on the TEE vendor and inherits TEE attacks (scope limitation, theoretical argument, in Attestable Audits; https://trustbutveri.fyi/implementations/attestable-audits/evidence/flaws/1/) [1]. Inherited finding. The prototype trusts AWS Nitro, not the Intel TDX or AMD SEV-SNP attestation roots targeted by the cited confidential-VM studies. Those studies are class context, not a demonstrated attack on this Nitro prototype. The design depends on trusting the TEE vendor, AWS in the prototype. The authors cite memory-aliasing, ciphertext side-channel and malicious-interrupt attacks on confidential VMs (BadRAM, CIPHERLEAKS, Heckler). Their answer is to revoke vulnerable base images once such attacks are discovered. Related finding: https://trustbutveri.fyi/mechanisms/tee-remote-attestation/evidence/flaws/5/.

  Response: The authors propose revoking vulnerable base images; they do not report a red-team evaluation of the prototype.
- CPU-only enclaves force small, quantized models and high cost (scope limitation, open question, in Attestable Audits; https://trustbutveri.fyi/implementations/attestable-audits/evidence/flaws/3/) [1][2]. Memory limits required 4-bit quantization, and the quantized model scored 51.4% on zero-shot MMLU. CPU inference cost 21.7 times as much per token as GPU inference, and the enclave roughly doubled the CPU cost. The authors wrote that H100 confidential computing had no multi-GPU support. NVIDIA's white paper of August 2025 describes a protected-PCIe mode that passes all eight GPUs of a Hopper HGX node to one confidential VM, with NVLink traffic unencrypted.
- Software-read telemetry can be forged by the operator (scope limitation, theoretical argument, in On-chip telemetry from timing, memory and performance counters; https://trustbutveri.fyi/mechanisms/on-chip-telemetry/evidence/flaws/1/) [11][13]. NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized.

  Related mechanism: Hardware-enabled guarantees (flexHEG) and guarantee processors (R1, not in the proposal). A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing.
- Timing challenges do not identify the individual chip (scope limitation, theoretical argument, in On-chip telemetry from timing, memory and performance counters; https://trustbutveri.fyi/mechanisms/on-chip-telemetry/evidence/flaws/3/) [11]. GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use.

**Open questions**

- Prompt-based model exfiltration is a residual gap (open question, open question, in Attestable Audits; https://trustbutveri.fyi/implementations/attestable-audits/evidence/flaws/2/) [1]. The authors state that "prompt-based model exfiltration during the user interaction step remains a residual gap".
- No quantified error rates or formal thresholds for timing primitives (open question, open question, in On-chip telemetry from timing, memory and performance counters; https://trustbutveri.fyi/mechanisms/on-chip-telemetry/evidence/flaws/5/) [11]. Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work.


## Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open failure or a dependency. Pointers, not recommendations: each brings its own readiness level and findings, and none is claimed to close a failure.

- **TEE remote attestation for AI workloads** (Operational use (legacy code R3), assessed for showing which software ran to a party that distrusts the operator holding the hardware)
  - Hardware-attested weight binding waits on it: The prototype needs porting to GPU confidential computing to handle larger models; the authors expect an overhead as small as 5 times there.
  - On-chip telemetry from timing, memory and performance counters depends on it.
- **Hardware-enabled guarantees (flexHEG) and guarantee processors** (Proposed (legacy code R1), assessed for checking and enforcing training-compute limits on chips, against adversaries up to states)
  - On-chip telemetry from timing, memory and performance counters waits on it: Shipping accelerators need a tamper-resistant, authenticated telemetry path.


## Dependencies

**Missing prerequisites**

- TEE remote attestation for AI workloads (Operational use (legacy code R3), assessed for showing which software ran to a party that distrusts the operator holding the hardware), needed by Hardware-attested weight binding and On-chip telemetry from timing, memory and performance counters

**Shared foundations**

- TEE remote attestation for AI workloads, relied on by Hardware-attested weight binding and On-chip telemetry from timing, memory and performance counters

**Blockers**

- Hardware-attested weight binding: The prototype needs porting to GPU confidential computing to handle larger models; the authors expect an overhead as small as 5 times there. (performance & compatibility; waits on TEE remote attestation for AI workloads) [1]
- Hardware-attested weight binding: As of September 2026 no code has been released for the prototype. (adversarial validation) [1]
- On-chip telemetry from timing, memory and performance counters: Shipping accelerators need a tamper-resistant, authenticated telemetry path. (hardware trust; waits on Hardware-enabled guarantees (flexHEG) and guarantee processors) [12][13]
- On-chip telemetry from timing, memory and performance counters: NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. (privacy & leakage) [2][10]
- On-chip telemetry from timing, memory and performance counters: Continuous challenge puzzles cost power and throughput on production workloads. (performance & compatibility) [11]
- On-chip telemetry from timing, memory and performance counters: Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. (adversarial validation) [13]


## What the verifier sees

- Model weights: shown by none; depends on the design for On-chip telemetry from timing, memory and performance counters; hidden by none; not involved in none; unspecified for Hardware-attested weight binding.
- Inputs and outputs: shown by none; depends on the design for On-chip telemetry from timing, memory and performance counters; hidden by none; not involved in none; unspecified for Hardware-attested weight binding.
- Training data: shown by none; depends on the design for On-chip telemetry from timing, memory and performance counters; hidden by none; not involved in none; unspecified for Hardware-attested weight binding.

## Implementations

- Hardware-attested weight binding: [Attestable Audits](https://trustbutveri.fyi/implementations/attestable-audits/) (R2, research prototype); [PAL*M](https://trustbutveri.fyi/implementations/palm/) (R2, research prototype); [Tinfoil model identity (Modelwrap)](https://trustbutveri.fyi/implementations/tinfoil-model-identity/) (R3, product)
- On-chip telemetry from timing, memory and performance counters: none on the map

## Sources

1. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). https://arxiv.org/abs/2506.23706
2. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). https://docs.nvidia.com/nvidia-secure-ai-with-blackwell-and-hopper-gpus-whitepaper.pdf
3. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). https://tee.fail/
4. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). https://batteringram.eu/
5. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). https://rmpocalypse.github.io/
6. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). https://www.amd.com/en/resources/product-security/bulletin/amd-sb-3020.html
7. A primer on secure enclaves, Tinfoil (2026). https://docs.tinfoil.sh/verification/secure-enclave-primer
8. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). https://arxiv.org/abs/2601.16199
9. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). https://tinfoil.sh/blog/2026-02-03-proving-model-identity
10. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). https://techgov.intelligence.org/blog/on-tees-for-privacy-preserving-monitoring-in-ai-governance
11. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). https://arxiv.org/abs/2602.09369
12. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). https://openreview.net/forum?id=uc79kOv0MV
13. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). https://arxiv.org/abs/2606.19262