# AI verification proposal A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-09. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0014,M-0019&implementations=M-0014:I-0010 How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's development status, security evidence and findings. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and findings) and https://trustbutveri.fyi/about/readiness/ (development status). ## Filters Filters apply to mechanisms only and describe the setting the proposal is for. None set. Every mechanism on the map was available. ## Overview One row per mechanism, read from its record. Open failures: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees. Findings are grouped as known failures, scope limitations and open questions. Only known failures count as failures. Counts are an inventory of published findings, not a risk score. | Mechanism | Development | Security evidence | Prover | Attack testing | Hardware | Open failures | Weights | Inputs and outputs | Training data | | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | | Bandwidth limits and compartmentalization / RAND secure inference data center (SIDC) design | Proposed | Published security analysis | Semi-trusted | Analysis | Retrofit device | 0 / 0 / 0 | unspecified | unspecified | unspecified | | Chip registries and manufacturing records | Proposed | Published security analysis | Semi-trusted | Analysis | Existing features | 0 / 1 / 0 | not involved | not involved | not involved | ## Claims No claims chosen. ## Mechanisms ### Bandwidth limits and compartmentalization A RAND design for a purpose-built facility that serves already-trained AI models while protecting weights and inference data against state-level attackers. ([Bandwidth limits and compartmentalization](https://trustbutveri.fyi/mechanisms/bandwidth-limits-and-compartmentalization/)) - Assessment: selected implementation [RAND secure inference data center (SIDC) design](https://trustbutveri.fyi/implementations/rand-secure-inference-data-centers/). - Development: Proposed (legacy code R1), assessed for the operator's own weight security, with no outside verification described. - Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed. - Claims in this proposal: none of them. - Threat model: semi-trusted prover. Hardware: retrofit device. Prover cooperation: required. Attack testing: analysis. Category: Isolation & system architectures. - What the verifier sees: model weights unspecified; inputs and outputs unspecified; training data unspecified. This Explorer has no asset-specific exposure assessment for this implementation. Check its source and deployment assumptions. ### Chip registries and manufacturing records Recording each AI chip's identity and owner from the fab onwards, and cryptographically fixing manufacturing records, so that chips can be accounted for later. ([Chip registries and manufacturing records](https://trustbutveri.fyi/mechanisms/chip-registries-and-manufacturing-records/)) - Assessment: mechanism family. - Development: Proposed (legacy code R1), assessed for a checkable record of which chips were made and who declared owning them. - Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed. - Claims in this proposal: none of them. - Threat model: semi-trusted prover. Hardware: existing features. Prover cooperation: required. Attack testing: analysis. Category: Compute accounting & provenance. - What the verifier sees: model weights not involved; inputs and outputs not involved; training data not involved. Records chip identities and owners; it does not handle model data. ## Properties **No new hardware needed** - Chip registries and manufacturing records ## Attack testing Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure. **Testing history** - Bandwidth limits and compartmentalization / RAND secure inference data center (SIDC) design: Analysis - Chip registries and manufacturing records: Analysis ## Limits **Open significant failures** - Documents and serial numbers can be forged (known failure, theoretical argument, in Chip registries and manufacturing records; https://trustbutveri.fyi/mechanisms/chip-registries-and-manufacturing-records/evidence/flaws/2/) [7]. Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. **Family finding context** - Context for RAND secure inference data center (SIDC) design. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there. Low-communication training reduces the bandwidth training needs (open question, theoretical argument, in Bandwidth limits and compartmentalization; https://trustbutveri.fyi/mechanisms/bandwidth-limits-and-compartmentalization/evidence/flaws/1/) [2][3][4]. DiLoCo matched fully synchronous training on 8 workers while communicating 500 times less. Rahman writes that this family of methods theoretically allows large-scale training with less than 100 Mbps. Lucid includes these methods in its bounds, but notes that extreme activation compression, architectures with unusually small inter-layer widths, or modular paradigms could erode the margin. - Context for RAND secure inference data center (SIDC) design. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there. Operator control of pod routing collapses the bound (known failure, theoretical argument, in Bandwidth limits and compartmentalization; https://trustbutveri.fyi/mechanisms/bandwidth-limits-and-compartmentalization/evidence/flaws/2/) [4]. Lucid's analysis finds that if the operator can freely assign pods to routers, it could dedicate a whole cell of 100 or more pods to one pipeline stage. The bound then falls to about 90–220x uncompressed and as low as about 25x with compression. The proposed mitigation, auditor-controlled random assignment that is periodically re-randomized, has not been implemented. - Context for RAND secure inference data center (SIDC) design. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there. Undeclared local storage raises per-pod capacity (scope limitation, theoretical argument, in Bandwidth limits and compartmentalization; https://trustbutveri.fyi/mechanisms/bandwidth-limits-and-compartmentalization/evidence/flaws/3/) [4]. More memory or storage per pod helps an adversary. Lucid requires per-pod storage to be declared, capped and physically inspected. - Context for RAND secure inference data center (SIDC) design. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there. Training within one pod is not covered (scope limitation, open question, in Bandwidth limits and compartmentalization; https://trustbutveri.fyi/mechanisms/bandwidth-limits-and-compartmentalization/evidence/flaws/4/) [4]. Lucid's bounds concern pre-training models larger than the pods are sized for. Training models that fit in one pod, fine-tuning and reinforcement-learning post-training within one pod are outside the modelled threat. - Context for RAND secure inference data center (SIDC) design. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there. Parallel scale-up switches are hard enforcement points (known failure, theoretical argument, in Bandwidth limits and compartmentalization; https://trustbutveri.fyi/mechanisms/bandwidth-limits-and-compartmentalization/evidence/flaws/5/) [5]. In GB200 topologies, GPUs reach GPUs in other nodes through NVSwitches without a NIC on the path. Amodo notes that limits are hard to enforce there because many switches work in parallel, so compromising one or two would bypass the limit. **Scope limitations** - Everything rests on the trusted setup (scope limitation, theoretical argument, in RAND secure inference data center (SIDC) design; https://trustbutveri.fyi/implementations/rand-secure-inference-data-centers/evidence/flaws/1/) [1]. Reference measurements for model weights and reference data are established in a trusted setup phase. The report states that the system cannot detect compromise that happened before ingestion if the trusted setup itself is compromised. - Security weakens over long operation (scope limitation, theoretical argument, in RAND secure inference data center (SIDC) design; https://trustbutveri.fyi/implementations/rand-secure-inference-data-centers/evidence/flaws/2/) [1]. The authors claim that the facility can withstand attacks at the OC5 level for a five-year operational period. They expect its ability to withstand long OC5 campaigns to become less robust the longer the facility remains in operation. - Records cover only chips that were recorded (scope limitation, theoretical argument, in Chip registries and manufacturing records; https://trustbutveri.fyi/mechanisms/chip-registries-and-manufacturing-records/evidence/flaws/1/) [8][10]. A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. Related mechanism: Remote detection of data centres (R1, not in the proposal). Looks for large data centres that were never declared, which a registry cannot show. - Insiders could alter records before they are fixed (scope limitation, theoretical argument, in Chip registries and manufacturing records; https://trustbutveri.fyi/mechanisms/chip-registries-and-manufacturing-records/evidence/flaws/3/) [8]. Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. **Not yet demonstrated** - Bandwidth limits and compartmentalization: Proposed (legacy code R1), assessed for the operator's own weight security, with no outside verification described - Chip registries and manufacturing records: Proposed (legacy code R1), assessed for a checkable record of which chips were made and who declared owning them ## Possible additions Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open failure or a dependency. Pointers, not recommendations: each brings its own readiness level and findings, and none is claimed to close a failure. None found. ## Dependencies **Blockers** - Bandwidth limits and compartmentalization: No prototype exists; RAND recommends prototyping key security features and integration now. (adversarial validation) [1] - Bandwidth limits and compartmentalization: The report describes internal integrity checks, audit logging and accreditation, but no way for a party outside the operator to verify the facility's properties. (access & governance) [1] - Bandwidth limits and compartmentalization: Human review of every prompt and response makes each request take three to five minutes, with the review steps as the rate-limiting factor. (performance & compatibility) [1] - Bandwidth limits and compartmentalization: Detailed design information is withheld from the public report and is to be evaluated privately with stakeholders, which limits independent public scrutiny. (access & governance) [1] - Chip registries and manufacturing records: No implementation of an AI chip registry has been publicly reported, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. (access & governance) [6][7] - Chip registries and manufacturing records: Linking records to physical chips needs hard-to-spoof unique IDs and inspections. (hardware trust) [6][7][8] - Chip registries and manufacturing records: Chips produced before a registry starts must be reconstructed from supplier records. (coverage & hidden compute) [8][10] ## What the verifier sees - Model weights: shown by none; depends on the design for none; hidden by none; not involved in Chip registries and manufacturing records; unspecified for Bandwidth limits and compartmentalization. - Inputs and outputs: shown by none; depends on the design for none; hidden by none; not involved in Chip registries and manufacturing records; unspecified for Bandwidth limits and compartmentalization. - Training data: shown by none; depends on the design for none; hidden by none; not involved in Chip registries and manufacturing records; unspecified for Bandwidth limits and compartmentalization. ## Implementations - Bandwidth limits and compartmentalization: [AI 2040 inference-only verification stack](https://trustbutveri.fyi/implementations/ai-2040-inference-only-verification-plan/) (R1, proposed architecture); [RAND secure inference data center (SIDC) design](https://trustbutveri.fyi/implementations/rand-secure-inference-data-centers/) (R1, proposed architecture) - Chip registries and manufacturing records: none on the map ## Sources 1. Highly Secure Inference Data Centers: A Vertically Integrated Strategy for Security Engineering, S. F. Comer et al. (2026). https://www.rand.org/pubs/research_reports/RRA4827-1.html 2. DiLoCo: Distributed Low-Communication Training of Language Models, A. Douillard et al. (2024). https://arxiv.org/abs/2311.08105 3. Does Distributed Training Undermine Compute Governance?, R. Rahman (2026). https://arxiv.org/abs/2605.29359 4. Traffic Shaping for Workload Classification, Lucid Computing (2026). https://lucidcomputing.substack.com/p/traffic-shaping-for-workload-classification 5. The Tray as a Bandwidth Boundary, Amodo Design (2026). https://amododesign.com/notes/2026-03-16-dpu-bandwidth-limiter/ 6. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). https://www.rand.org/pubs/working_papers/WRA4077-1.html 7. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). https://www.iaps.ai/research/near-term-verification-methods-for-ai-chip-exports 8. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). https://nacicankaya.substack.com/p/tsmc-most-definitely-has-a-golden 9. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). https://arxiv.org/abs/2604.04712 10. Covert AI Projects, B. Halstead & T. Larsen (2026). https://ai-2040.com/supplements/covert-ai-projects