# AI verification proposal

A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-09. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0013,M-0016&implementations=M-0016:I-0020

How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's development status, security evidence and findings. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and findings) and https://trustbutveri.fyi/about/readiness/ (development status).

## Filters

Filters apply to mechanisms only and describe the setting the proposal is for.

None set. Every mechanism on the map was available.

## Overview

One row per mechanism, read from its record. Open failures: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees. Findings are grouped as known failures, scope limitations and open questions. Only known failures count as failures. Counts are an inventory of published findings, not a risk score.

| Mechanism | Development | Security evidence | Prover | Attack testing | Hardware | Open failures | Weights | Inputs and outputs | Training data |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Network taps and certifiers | Proposed | Published security analysis | Adversarial | Analysis | Retrofit device | 0 / 2 / 0 | depends | depends | depends |
| Timed challenge-response and memory-occupation challenges / Data-centre memory challenging | Proposed | Published security analysis | Adversarial | Analysis | Retrofit device | 0 / 1 / 0 | unspecified | unspecified | unspecified |

## Claims

No claims chosen.

## Mechanisms

### Network taps and certifiers

Devices on a cluster's network links that copy and hash all traffic, so a verifier can later check sampled records against declared work. ([Network taps and certifiers](https://trustbutveri.fyi/mechanisms/network-taps-and-certifiers/))

- Assessment: mechanism family.
- Development: Proposed (legacy code R1), assessed for committing a complete record of cluster traffic, so declared inference can be checked.
- Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: retrofit device. Prover cooperation: required. Attack testing: analysis. Category: Off-chip devices & sensors.
- What the verifier sees: model weights depends; inputs and outputs depends; training data depends. Only hashes leave the site; records picked for a challenge are opened for replay at a verification facility.

### Timed challenge-response and memory-occupation challenges

A proposed design that times answers from a data centre's memory to check that declared data is present or that no free memory remains. ([Timed challenge-response and memory-occupation challenges](https://trustbutveri.fyi/mechanisms/timed-challenge-response/))

- Assessment: selected implementation [Data-centre memory challenging](https://trustbutveri.fyi/implementations/data-centre-memory-challenging/).
- Development: Proposed (legacy code R1), assessed for confirming data presence and bounding free memory across data-centre servers.
- Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: retrofit device. Prover cooperation: required. Attack testing: analysis. Category: Cryptographic & computational.
- What the verifier sees: model weights unspecified; inputs and outputs unspecified; training data unspecified. This Explorer has no asset-specific exposure assessment for this implementation. Check its source and deployment assumptions.


## Properties

**Built for an adversarial prover**

- Network taps and certifiers
- Timed challenge-response and memory-occupation challenges

**Failures since mitigated**

- Verifier dictionary attacks on hashes (in Network taps and certifiers) [1]


## Attack testing

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

**Testing history**

- Network taps and certifiers: Analysis
- Timed challenge-response and memory-occupation challenges / Data-centre memory challenging: Analysis


## Limits

**Open significant failures**

- Output nondeterminism leaves covert capacity (known failure, theoretical argument, in Network taps and certifiers; https://trustbutveri.fyi/mechanisms/network-taps-and-certifiers/evidence/flaws/1/) [1][9]. Hashing cannot remove information hidden in the outputs themselves. The Secure Gateway Device paper estimates that about 0.1 bit per token remains even with seed-synchronized replay checks. For a 200k-GPU inference cluster at full load (2,000 tokens per GPU per second), that is about 40 Mbit/s of covert egress, enough to move a 1 TB model in under three days. The paper names this the core remaining challenge and points to deterministic replay or active scrubbing of hardware-induced entropy. An independent study found that an adversary who chooses the prompts roughly doubles the bits leaked per token under Gumbel-based inference verification; see Bounding unexplained information in outputs.

  Related mechanism: Deterministic and bit-exact inference (R3, not in the proposal). Deterministic replay is one of the two remedies the flaw's source names.

  Related mechanism: Bounding unexplained information in outputs (R2, not in the proposal). Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict.
- Residual side channels in simple passive setups (known failure, theoretical argument, in Network taps and certifiers; https://trustbutveri.fyi/mechanisms/network-taps-and-certifiers/evidence/flaws/4/) [5]. Amodo's analysis of its own tapped prototype lists unvalidated header fields, timing of permitted traffic and variation in response formatting as residual channels, and concludes that the passive tap must be replaced by an active one.
- Remote memory narrows the timing margin (known failure, theoretical argument, in Data-centre memory challenging; https://trustbutveri.fyi/implementations/data-centre-memory-challenging/evidence/flaws/1/) [3]. A remote memory access round trip takes about 1–2 µs over InfiniBand or RoCE, against about 70–200 ns for a local DRAM read. The overview says verification of memory saturation depends on ruling out remote access, by response latency or by physical disconnection.

**Family finding context**

- Context for Data-centre memory challenging. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there. Timing-based software attestation has been broken in practice (known failure, demonstrated attack, in Timed challenge-response and memory-occupation challenges; https://trustbutveri.fyi/mechanisms/timed-challenge-response/evidence/flaws/1/) [11][12]. Castelluccia et al. implemented two generic attacks, one based on a return-oriented rootkit and one on code compression, together with specific attacks on SWATT and ICE-based schemes, on commodity sensor nodes. They conclude that secure time-based attestation is "very difficult, if not impossible, to design correctly". The attacks target embedded schemes, not AI accelerators.

  Response: Perrig and van Doorn, two of the designers of SWATT and ICE, replied in August 2010. They argue that the rootkit attack defeats a naive implementation, not a property the schemes claim, and that the SWATT attack was run on a re-implementation on a chip with eight times the program memory, where SWATT's own chip is almost always full of code. They accept that the attack on ICE works.
- Context for Data-centre memory challenging. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there. Remote memory narrows the timing margin (known failure, theoretical argument, in Timed challenge-response and memory-occupation challenges; https://trustbutveri.fyi/mechanisms/timed-challenge-response/evidence/flaws/2/) [3]. Data-centre remote memory access returns in about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview says verification of memory saturation depends on ruling out remote access by latency or physical disconnection. It names pre-staging data into local memory as the remaining evasion and proposes an unpredictable, capacity-filling challenge to close it.

  Related mechanism: Bandwidth limits and compartmentalization (R2, not in the proposal). Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced.
- Context for Data-centre memory challenging. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there. Error rates not quantified (open question, open question, in Timed challenge-response and memory-occupation challenges; https://trustbutveri.fyi/mechanisms/timed-challenge-response/evidence/flaws/3/) [13]. Monfared et al. show separable timing distributions. Their acceptance rule passes a GPU when its mean time per round stays at or below a chosen maximum, and an appendix outlines statistical tests for the proof-of-work puzzle. They leave hardware-specific threshold values to future work and report no false-positive or false-negative rates.

**Scope limitations**

- Some links cannot be passively tapped (scope limitation, open question, in Network taps and certifiers; https://trustbutveri.fyi/mechanisms/network-taps-and-certifiers/evidence/flaws/2/) [2][10]. Cankaya notes that copper-connected scale-up domains (for example NVL72 racks and TPU v7 cubes) are much harder to tap than fibre, and that optical budgets make passive taps impractical on 400GBASE-SR8 multimode links. Amodo found no taps advertised for 53 GBaud links as of May 2026.
- Encrypted fabrics hide plaintext from both parties (scope limitation, open question, in Network taps and certifiers; https://trustbutveri.fyi/mechanisms/network-taps-and-certifiers/evidence/flaws/3/) [2]. Cankaya notes that with TEE-protected sessions whose keys are ephemeral and managed inside the TEE, neither the operator nor the manufacturer can recover session keys after the session, so tapped traffic could not be opened for recomputation. For other encrypted fabrics, the operator can retain keys.
- Completeness rests on physical monitoring left out of scope (scope limitation, open question, in Network taps and certifiers; https://trustbutveri.fyi/mechanisms/network-taps-and-certifiers/evidence/flaws/5/) [1]. The Secure Gateway Device paper assumes the facility is physically monitored, and states that the whole architecture depends on the device being the only communication channel. It names radio emanation, power-line signalling and thermal channels as covert channels beyond that scope.

  Related mechanism: Side-channel suppression for isolated facilities (R1, not in the proposal). Addresses the radio, power-line and thermal channels that network-level designs leave out.
- Presence does not show absence (scope limitation, theoretical argument, in Data-centre memory challenging; https://trustbutveri.fyi/implementations/data-centre-memory-challenging/evidence/flaws/2/) [3]. A check that data is present does not show that nothing else is stored. The overview names pre-staging data into local memory before a challenge as the remaining evasion, and proposes an unpredictable, capacity-filling challenge to close it.

**Not yet demonstrated**

- Network taps and certifiers: Proposed (legacy code R1), assessed for committing a complete record of cluster traffic, so declared inference can be checked
- Timed challenge-response and memory-occupation challenges: Proposed (legacy code R1), assessed for confirming data presence and bounding free memory across data-centre servers


## Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open failure or a dependency. Pointers, not recommendations: each brings its own readiness level and findings, and none is claimed to close a failure.

- **Deterministic and bit-exact inference** (Operational use (legacy code R3), assessed for reproducing open-model inference from receipts in Gensyn's information-market service)
  - Bears on the open significant failure "Output nondeterminism leaves covert capacity" in Network taps and certifiers. Deterministic replay is one of the two remedies the flaw's source names.
  - Network taps and certifiers waits on it: Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove.
- **Bounding unexplained information in outputs** (Research demonstration (legacy code R2), assessed for bounding how much hidden information can leave in checked inference outputs)
  - Bears on the open significant failure "Output nondeterminism leaves covert capacity" in Network taps and certifiers. Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict.
- **Bandwidth limits and compartmentalization** (Research demonstration (legacy code R2), assessed for monitoring inter-node traffic with operator-run software on four GPUs)
  - Timed challenge-response and memory-occupation challenges waits on it: Remote memory access must be excluded during challenges.
- **Tamper evidence for verifier devices** (Research demonstration (legacy code R2), assessed for detecting probing of proposed verifier hardware, using server and electronics prototypes as evidence)
  - Network taps and certifiers waits on it: Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them.
- **Side-channel suppression for isolated facilities** (Proposed (legacy code R1), assessed for bounding physical covert channels out of a verified enclosure)
  - Network taps and certifiers waits on it: Radio, power-line and thermal channels are not addressed by network-level designs.
- **Sampled inference recomputation** (Operational use (legacy code R3), assessed for checking untrusted workers' activations against the declared model, prompt and precision)
  - Network taps and certifiers depends on it.


## Dependencies

**Missing prerequisites**

- Sampled inference recomputation (Operational use (legacy code R3), assessed for checking untrusted workers' activations against the declared model, prompt and precision), needed by Network taps and certifiers
- Deterministic and bit-exact inference (Operational use (legacy code R3), assessed for reproducing open-model inference from receipts in Gensyn's information-market service), needed by Network taps and certifiers
- Tamper evidence for verifier devices (Research demonstration (legacy code R2), assessed for detecting probing of proposed verifier hardware, using server and electronics prototypes as evidence), needed by Network taps and certifiers
- Side-channel suppression for isolated facilities (Proposed (legacy code R1), assessed for bounding physical covert channels out of a verified enclosure), needed by Network taps and certifiers
- Bandwidth limits and compartmentalization (Research demonstration (legacy code R2), assessed for monitoring inter-node traffic with operator-run software on four GPUs), needed by Timed challenge-response and memory-occupation challenges

**Blockers**

- Network taps and certifiers: No complete verification tap has been demonstrated at production frontend link rates, and on the tested CPU no hash algorithm reached line rate with minimum-size frames. (performance & compatibility) [10][14]
- Network taps and certifiers: Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove. (evidence binding; waits on Deterministic and bit-exact inference) [1]
- Network taps and certifiers: Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them. (hardware trust; waits on Tamper evidence for verifier devices) [1][3]
- Network taps and certifiers: Radio, power-line and thermal channels are not addressed by network-level designs. (coverage & hidden compute; waits on Side-channel suppression for isolated facilities) [1]
- Network taps and certifiers: Red-teaming by specialists is called for but has not been reported. (adversarial validation) [1]
- Timed challenge-response and memory-occupation challenges: No network-level probe has been shown to distinguish one server's memory contents from another's. (adversarial validation) [3]
- Timed challenge-response and memory-occupation challenges: Most of the design needs a probe in close proximity to the challenged memory. (access & governance) [3]
- Timed challenge-response and memory-occupation challenges: Filling a pod's volatile memory takes tens of minutes, and on-board SSDs take hours. (performance & compatibility) [3]
- Timed challenge-response and memory-occupation challenges: Remote memory access must be excluded during challenges. (coverage & hidden compute; waits on Bandwidth limits and compartmentalization) [3]


## What the verifier sees

- Model weights: shown by none; depends on the design for Network taps and certifiers; hidden by none; not involved in none; unspecified for Timed challenge-response and memory-occupation challenges.
- Inputs and outputs: shown by none; depends on the design for Network taps and certifiers; hidden by none; not involved in none; unspecified for Timed challenge-response and memory-occupation challenges.
- Training data: shown by none; depends on the design for Network taps and certifiers; hidden by none; not involved in none; unspecified for Timed challenge-response and memory-occupation challenges.

## Implementations

- Network taps and certifiers: [AI 2040 inference-only verification stack](https://trustbutveri.fyi/implementations/ai-2040-inference-only-verification-plan/) (R1, proposed architecture); [Low-trust AI compute verification system overview](https://trustbutveri.fyi/implementations/low-trust-compute-verification-system-overview/) (R1, proposed architecture); [SASH confidential network logger](https://trustbutveri.fyi/implementations/sash-confidential-network-logger/) (R1, research prototype)
- Timed challenge-response and memory-occupation challenges: [Data-centre memory challenging](https://trustbutveri.fyi/implementations/data-centre-memory-challenging/) (R1, proposed architecture); [GPU contention probes](https://trustbutveri.fyi/implementations/gpu-contention-probes/) (R2, research prototype); [Low-trust AI compute verification system overview](https://trustbutveri.fyi/implementations/low-trust-compute-verification-system-overview/) (R1, proposed architecture); [SAGE](https://trustbutveri.fyi/implementations/sage-gpu-attestation/) (R2, research prototype); [VRAM-residency challenge](https://trustbutveri.fyi/implementations/vram-residency-challenge/) (R2, research prototype)

## Sources

1. Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors, N. Cankaya et al. (2026). https://arxiv.org/abs/2606.10724
2. The Fundamentals and Feasibility of Secure Network Taps for Verifying AI Datacenter Use, N. Cankaya (2026). https://nacicankaya.substack.com/p/research-note-the-fundamentals-and
3. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). https://intelligence.org/wp-content/uploads/2026/06/A-system-overview-for-near-term-low-trust-AI-compute-verification.pdf
4. Verification Plan, R. Dean (2026). https://ai-2040.com/supplements/verification-plan
5. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). https://amododesign.com/notes/2026-09-15-network-tap-inference-verification/
6. Amodo-Design/Inference-Recomputation-Prototype (GitHub repository), Amodo Design (2026). https://github.com/Amodo-Design/Inference-Recomputation-Prototype
7. inference-verification: Inference Verification Prototype, Singapore AI Safety Hub (SASH) (2026). https://github.com/sg-ai-safety-hub/inference-verification
8. Internationalising AI Verification, Singapore AI Safety Hub (SASH) (2026). https://www.aisafety.sg/research/internationalising-ai-verification
9. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). https://arxiv.org/abs/2608.23375
10. Network Tapping for AI Verification: A Technical Assessment, Amodo Design (2026). https://amododesign.com/notes/2026-05-03-network-tapping/
11. On the Difficulty of Software-Based Attestation of Embedded Devices, C. Castelluccia et al. (2009). https://s3.eurecom.fr/docs/ccs09_Castelluccia.pdf
12. Refutation of "On the Difficulty of Software-Based Attestation of Embedded Devices", A. Perrig & L. van Doorn (2010). https://netsec.ethz.ch/publications/papers/perrig-ccs-refutation.pdf
13. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). https://arxiv.org/abs/2602.09369
14. Network Traffic Hashing, Amodo Design (2026). https://amododesign.com/notes/2026-07-03-network-traffic-hashing/