# AI verification proposal A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-09. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0016&implementations=M-0016:I-0021 How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's development status, security evidence and findings. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and findings) and https://trustbutveri.fyi/about/readiness/ (development status). ## Filters Filters apply to mechanisms only and describe the setting the proposal is for. None set. Every mechanism on the map was available. ## Overview One row per mechanism, read from its record. Open failures: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees. Findings are grouped as known failures, scope limitations and open questions. Only known failures count as failures. Counts are an inventory of published findings, not a risk score. | Mechanism | Development | Security evidence | Prover | Attack testing | Hardware | Open failures | Weights | Inputs and outputs | Training data | | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | | Timed challenge-response and memory-occupation challenges / SAGE | Research demonstration | Published security analysis | Adversarial | Analysis | Existing features | 0 / 0 / 0 | unspecified | unspecified | unspecified | ## Claims No claims chosen. ## Mechanisms ### Timed challenge-response and memory-occupation challenges A software-only attestation scheme in which a GPU must compute a checksum over its own code within a time limit, without trusted GPU hardware. ([Timed challenge-response and memory-occupation challenges](https://trustbutveri.fyi/mechanisms/timed-challenge-response/)) - Assessment: selected implementation [SAGE](https://trustbutveri.fyi/implementations/sage-gpu-attestation/). - Development: Research demonstration (legacy code R2), assessed for attesting code execution on a GPU that lacks hardware trusted-execution support. - Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed. - Claims in this proposal: none of them. - Threat model: adversarial prover. Hardware: existing features. Prover cooperation: required. Attack testing: analysis. Category: Cryptographic & computational. - What the verifier sees: model weights unspecified; inputs and outputs unspecified; training data unspecified. This Explorer has no asset-specific exposure assessment for this implementation. Check its source and deployment assumptions. ## Properties **Built for an adversarial prover** - Timed challenge-response and memory-occupation challenges **No new hardware needed** - Timed challenge-response and memory-occupation challenges ## Attack testing Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure. **Testing history** - Timed challenge-response and memory-occupation challenges / SAGE: Analysis ## Limits **Family finding context** - Context for SAGE. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there. Timing-based software attestation has been broken in practice (known failure, demonstrated attack, in Timed challenge-response and memory-occupation challenges; https://trustbutveri.fyi/mechanisms/timed-challenge-response/evidence/flaws/1/) [2][3]. Castelluccia et al. implemented two generic attacks, one based on a return-oriented rootkit and one on code compression, together with specific attacks on SWATT and ICE-based schemes, on commodity sensor nodes. They conclude that secure time-based attestation is "very difficult, if not impossible, to design correctly". The attacks target embedded schemes, not AI accelerators. Response: Perrig and van Doorn, two of the designers of SWATT and ICE, replied in August 2010. They argue that the rootkit attack defeats a naive implementation, not a property the schemes claim, and that the SWATT attack was run on a re-implementation on a chip with eight times the program memory, where SWATT's own chip is almost always full of code. They accept that the attack on ICE works. - Context for SAGE. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there. Remote memory narrows the timing margin (known failure, theoretical argument, in Timed challenge-response and memory-occupation challenges; https://trustbutveri.fyi/mechanisms/timed-challenge-response/evidence/flaws/2/) [4]. Data-centre remote memory access returns in about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview says verification of memory saturation depends on ruling out remote access by latency or physical disconnection. It names pre-staging data into local memory as the remaining evasion and proposes an unpredictable, capacity-filling challenge to close it. Related mechanism: Bandwidth limits and compartmentalization (R2, not in the proposal). Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced. - Context for SAGE. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there. Error rates not quantified (open question, open question, in Timed challenge-response and memory-occupation challenges; https://trustbutveri.fyi/mechanisms/timed-challenge-response/evidence/flaws/3/) [5]. Monfared et al. show separable timing distributions. Their acceptance rule passes a GPU when its mean time per round stays at or below a chosen maximum, and an appendix outlines statistical tests for the proof-of-work puzzle. They leave hardware-specific threshold values to future work and report no false-positive or false-negative rates. **Scope limitations** - Self-modifying code limits the timing margin (scope limitation, open question, in SAGE; https://trustbutveri.fyi/implementations/sage-gpu-attestation/evidence/flaws/1/) [1]. The authors report that their implementation reaches 75% of maximum GPU utilisation when the checksum uses self-modifying code, and that this limits the time difference caused by an adversary who inserts instructions into the checksum loop. They note that other cache-eviction strategies could raise utilisation. ## Possible additions Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open failure or a dependency. Pointers, not recommendations: each brings its own readiness level and findings, and none is claimed to close a failure. None found. ## Dependencies **Blockers** - Timed challenge-response and memory-occupation challenges: The verifier must know the exact hardware configuration of the GPU. (hardware trust) [1] - Timed challenge-response and memory-occupation challenges: The verifier runs in an SGX enclave on the same host as the GPU, so the scheme inherits trust in that enclave. (hardware trust) [1] ## What the verifier sees - Model weights: shown by none; depends on the design for none; hidden by none; not involved in none; unspecified for Timed challenge-response and memory-occupation challenges. - Inputs and outputs: shown by none; depends on the design for none; hidden by none; not involved in none; unspecified for Timed challenge-response and memory-occupation challenges. - Training data: shown by none; depends on the design for none; hidden by none; not involved in none; unspecified for Timed challenge-response and memory-occupation challenges. ## Implementations - Timed challenge-response and memory-occupation challenges: [Data-centre memory challenging](https://trustbutveri.fyi/implementations/data-centre-memory-challenging/) (R1, proposed architecture); [GPU contention probes](https://trustbutveri.fyi/implementations/gpu-contention-probes/) (R2, research prototype); [Low-trust AI compute verification system overview](https://trustbutveri.fyi/implementations/low-trust-compute-verification-system-overview/) (R1, proposed architecture); [SAGE](https://trustbutveri.fyi/implementations/sage-gpu-attestation/) (R2, research prototype); [VRAM-residency challenge](https://trustbutveri.fyi/implementations/vram-residency-challenge/) (R2, research prototype) ## Sources 1. SAGE: Software-based Attestation for GPU Execution, A. Ivanov et al. (2023). https://www.usenix.org/conference/atc23/presentation/ivanov 2. On the Difficulty of Software-Based Attestation of Embedded Devices, C. Castelluccia et al. (2009). https://s3.eurecom.fr/docs/ccs09_Castelluccia.pdf 3. Refutation of "On the Difficulty of Software-Based Attestation of Embedded Devices", A. Perrig & L. van Doorn (2010). https://netsec.ethz.ch/publications/papers/perrig-ccs-refutation.pdf 4. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). https://intelligence.org/wp-content/uploads/2026/06/A-system-overview-for-near-term-low-trust-AI-compute-verification.pdf 5. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). https://arxiv.org/abs/2602.09369