# AI verification proposal

A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-08. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0018,M-0017&implementations=M-0017:I-0011

How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's readiness and open flaws. Readiness levels R0 to R4 describe one record's public evidence for its assessed use and are never combined. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and flaws) and https://trustbutveri.fyi/about/readiness/ (readiness levels).

## Filters

Filters apply to mechanisms only and describe the setting the proposal is for.

None set. Every mechanism on the map was available.

## Overview

One row per mechanism, read from its record. Open flaws: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees.

| Mechanism | Readiness | Prover | Attack testing | Hardware | Open flaws | Weights | Inputs and outputs | Training data |
| --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Chip location verification | R1 | Adversarial | Analysis | Existing features | 0 / 4 / 0 | not involved | not involved | not involved |
| Tamper evidence for verifier devices / AI 2040 inference-only verification stack | R1 | Adversarial | None | Retrofit device | 0 / 3 / 0 | unspecified | unspecified | unspecified |

## Claims

No claims chosen.

## Mechanisms

### Chip location verification

Timing a chip's signed replies to trusted servers at known places, so that the speed of light bounds how far away the chip can be. ([Chip location verification](https://trustbutveri.fyi/mechanisms/chip-location-verification/))

- Assessment: mechanism family.
- Readiness: R1 Proposed, assessed for bounding how far a chip is from trusted landmark servers when checked.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: existing features. Prover cooperation: required. Attack testing: analysis. Category: Compute accounting & provenance.
- What the verifier sees: model weights not involved; inputs and outputs not involved; training data not involved. Times signed replies from chips; it does not handle model data.

### Tamper evidence for verifier devices

A proposed retrofit that isolates data-centre inference units, taps their front-end traffic and recomputes random samples to check that only declared inference runs. ([Tamper evidence for verifier devices](https://trustbutveri.fyi/mechanisms/tamper-evidence-for-verifier-devices/))

- Assessment: selected implementation [AI 2040 inference-only verification stack](https://trustbutveri.fyi/implementations/ai-2040-inference-only-verification-plan/).
- Readiness: R1 Proposed, assessed for showing that retrofitted data centres run only inference.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: retrofit device. Prover cooperation: required. Attack testing: none. Category: Isolation & system architectures.
- What the verifier sees: model weights unspecified; inputs and outputs unspecified; training data unspecified. This Explorer has no asset-specific exposure assessment for this implementation. Check its source and deployment assumptions.


## Properties

**Built for an adversarial prover**

- Chip location verification
- Tamper evidence for verifier devices

**No new hardware needed**

- Chip location verification


## Attack testing

Published attempts to break a system, including those that found failures. Testing history does not establish that open flaws are resolved.

**Testing history**

- Chip location verification: Analysis


## Limits

**Open significant flaws**

- Extracting a chip's key lets another device answer for it (theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/#flaw-1) [1][6]. Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM.
- Added delay can shift an estimated position (demonstrated attack, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/#flaw-2) [1][4]. Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location.
- Faster-than-assumed network paths (theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/#flaw-3) [1][4]. Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often.
- Compromised landmarks can falsify measurements (theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/#flaw-4) [1][4][5]. A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators.
- The recomputation server must be trusted (theoretical argument, in AI 2040 inference-only verification stack; https://trustbutveri.fyi/implementations/ai-2040-inference-only-verification-plan/#flaw-1) [8][9][11]. The plan calls the integrity of the recomputation server an extremely important aspect, and its argument that sampling verifies all outputs assumes that the server's computations and outputs can be trusted. The companion page notes that the server sits inside the prover's facility, possibly under the prover's physical control, and that hardening it against integrity attacks needs significant research. Amodo rates recomputation-server security as not on track.
- Spare compute is not verified (theoretical argument, in AI 2040 inference-only verification stack; https://trustbutveri.fyi/implementations/ai-2040-inference-only-verification-plan/#flaw-2) [8]. The plan states that it does not verify that spare compute is unused for unapproved workloads, because this seems very challenging. It relies instead on side-channel bounds and memory wipes, so that the only results that persist are verified inference outputs.
- A recomputation family degrades against prompt-controlling adversaries (demonstrated attack, in AI 2040 inference-only verification stack; https://trustbutveri.fyi/implementations/ai-2040-inference-only-verification-plan/#flaw-3) [8][9][13][14]. The plan's companion page names DiFR among the recomputation schemes being tested. An independent study found that Gumbel-based inference verification, the family that includes Token-DiFR, leaks roughly twice as many bits per token when the adversary chooses prompts that disrupt the text's structure, across six models of 1 to 32 billion parameters. The slowdown it imposes on a hidden-signalling adversary falls from 146–254 times under benign prompts to 60–118 times. The attack weakens the bound on hidden information in outputs, which the plan relies on to keep undeclared results from leaving.

**Family finding context**

- Context for AI 2040 inference-only verification stack; applicability depends on the finding's scope. Seals are often defeated with simple methods (demonstrated attack, in Tamper evidence for verifier devices; https://trustbutveri.fyi/mechanisms/tamper-evidence-for-verifier-devices/#flaw-1) [15][16]. Mechanism-class evidence. Published defeats of general security seals. They warn about proposed verifier-device seals, but do not demonstrate defeat of an AI verification enclosure or sensor. In 1996 a Los Alamos vulnerability assessment defeated all 94 security seals it examined, with 132 defeats in total, using rapid, inexpensive, low-tech methods. It found that seal cost did not predict security. In 2001 Johnston reported that high-tech seals are often easier to defeat than low-tech ones.
- Context for AI 2040 inference-only verification stack; applicability depends on the finding's scope. Security depends on inspection protocols (theoretical argument, in Tamper evidence for verifier devices; https://trustbutveri.fyi/mechanisms/tamper-evidence-for-verifier-devices/#flaw-2) [16][17]. Mechanism-class evidence. An inspection and protocol requirement drawn from safeguards and enclosure studies, not a reported break of a deployed AI verifier. Johnston argues that a seal is no better than the protocols for using it, and that inspectors are usually given little useful information on how to detect tampering. The Sandia survey notes that larger enclosures are hard to inspect fully and that sensor data must be authenticated.
- Context for AI 2040 inference-only verification stack; applicability depends on the finding's scope. Attack classes outside published models (open question, in Tamper evidence for verifier devices; https://trustbutveri.fyi/mechanisms/tamper-evidence-for-verifier-devices/#flaw-3) [18][19][20]. Mechanism-class evidence. The radio compensation result is emulated using measured channel data under a known-reference attacker model. It is not a physical bypass demonstration against an AI verifier enclosure. The authors of the batteryless cover say they cannot assess chemical-solvent attacks, which exceed their expertise, and deem cover removal impractical. Anti-Tamper Radio's reference can drift as the environment or measurement system ages; the authors suggest gradually renewing the reference. A 2025 follow-up by some of the same authors shows, by emulation on measured channel data, that an attacker who knows the reference channel and the needle's effect on it could inject a signal that cancels the change caused by a needle insertion. It proposes a reconfigurable intelligent surface that randomizes the channel as a countermeasure.

**Not yet demonstrated**

- Chip location verification: R1 Proposed, assessed for bounding how far a chip is from trusted landmark servers when checked
- Tamper evidence for verifier devices: R1 Proposed, assessed for showing that retrofitted data centres run only inference


## Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open flaw or a dependency. Pointers, not recommendations: each brings its own readiness level and flaws, and none is claimed to close a flaw.

- **Memory wiping and proofs of secure erasure** (R1 Proposed, assessed for showing that no data from earlier work persists in memory the wipe reaches)
  - Tamper evidence for verifier devices waits on it: Memory wiping may use existing algorithms, but hardware testing is at an early stage.
- **Network taps and certifiers** (R1 Proposed, assessed for committing a complete record of cluster traffic, so declared inference can be checked)
  - Tamper evidence for verifier devices waits on it: Passive optical taps work at 400G, but the 800G and 1600G line rates now arriving in data centres are undemonstrated.
- **Side-channel suppression for isolated facilities** (R1 Proposed, assessed for bounding physical covert channels out of a verified enclosure)
  - Tamper evidence for verifier devices waits on it: There is no plan yet for quickly scaling side-channel defences on a frontier cluster; only early theoretical pieces exist.
- **Whole-workload recomputation (reproducible packets)** (R1 Proposed, assessed for recomputing whole workloads to show a cluster runs only declared inference)
  - Tamper evidence for verifier devices waits on it: A fully reproducible inference stack needs substantial software and tooling, and per-packet network reproducibility may need considerable software, firmware and possibly hardware work.
- **Sampled inference recomputation** (R3 In production, assessed for checking untrusted workers' activations against the declared model, prompt and precision)
  - Tamper evidence for verifier devices depends on it.
- **TEE remote attestation for AI workloads** (R3 In production, assessed for showing which software ran to a party that distrusts the operator holding the hardware)
  - Chip location verification depends on it.


## Dependencies

**Missing prerequisites**

- TEE remote attestation for AI workloads (R3 In production, assessed for showing which software ran to a party that distrusts the operator holding the hardware), needed by Chip location verification
- Sampled inference recomputation (R3 In production, assessed for checking untrusted workers' activations against the declared model, prompt and precision), needed by Tamper evidence for verifier devices
- Whole-workload recomputation (reproducible packets) (R1 Proposed, assessed for recomputing whole workloads to show a cluster runs only declared inference), needed by Tamper evidence for verifier devices

**Blockers**

- Chip location verification: No public code or reproducible end-to-end location results are available for the reported H100 prototype. (adversarial validation) [2][3]
- Chip location verification: Per-chip keys must be provisioned and protected against extraction; hardware-integrated, tamper-resistant versions still need R&D. (hardware trust) [1][6][21]
- Chip location verification: The time limit forces a trade-off: a limit at the speed of light in fibre can be beaten by faster links, while one at the vacuum speed of light makes honest chips fail often. (protocol soundness) [1]
- Chip location verification: A trusted landmark network must be built and secured, and who should operate it, under what oversight, is unsettled. (access & governance) [1][4]
- Tamper evidence for verifier devices: A fully reproducible inference stack needs substantial software and tooling, and per-packet network reproducibility may need considerable software, firmware and possibly hardware work. (performance & compatibility; waits on Whole-workload recomputation (reproducible packets)) [9]
- Tamper evidence for verifier devices: Passive optical taps work at 400G, but the 800G and 1600G line rates now arriving in data centres are undemonstrated. (performance & compatibility; waits on Network taps and certifiers) [9]
- Tamper evidence for verifier devices: Checking that taps are correctly installed and stay in place at scale is not a solved problem, and hardening the recomputation server inside the prover's facility needs significant research. (hardware trust; waits on Tamper evidence for verifier devices) [9][11]
- Tamper evidence for verifier devices: There is no plan yet for quickly scaling side-channel defences on a frontier cluster; only early theoretical pieces exist. (coverage & hidden compute; waits on Side-channel suppression for isolated facilities) [9]
- Tamper evidence for verifier devices: Memory wiping may use existing algorithms, but hardware testing is at an early stage. (coverage & hidden compute; waits on Memory wiping and proofs of secure erasure) [9]
- Tamper evidence for verifier devices: Robust red-teaming of recomputation schemes has not started, and most algorithm development remains academic. (adversarial validation) [9][11]


## What the verifier sees

- Model weights: shown by none; depends on the design for none; hidden by none; not involved in Chip location verification; unspecified for Tamper evidence for verifier devices.
- Inputs and outputs: shown by none; depends on the design for none; hidden by none; not involved in Chip location verification; unspecified for Tamper evidence for verifier devices.
- Training data: shown by none; depends on the design for none; hidden by none; not involved in Chip location verification; unspecified for Tamper evidence for verifier devices.

## Implementations

- Chip location verification: [Lucid sovereignty (location) certificates](https://trustbutveri.fyi/implementations/lucid-location-certificates/) (R1, standard)
- Tamper evidence for verifier devices: [AI 2040 inference-only verification stack](https://trustbutveri.fyi/implementations/ai-2040-inference-only-verification-plan/) (R1, proposed architecture)

## Sources

1. Location Verification for AI Chips, A. Brass & O. Aarne (2024). https://www.iaps.ai/research/location-verification-for-ai-chips
2. Location Verification for AI Chips (issue brief), A. Brass (2025). https://static1.squarespace.com/static/64edf8e7f2b10d716b5ba0e1/t/6827b67275666f3757f134ea/1747433075281/Location+Verification+two-pager.pdf
3. Ping-based Location, Ulyssean (2025). https://ping-location.info/
4. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). https://www.iaps.ai/research/near-term-verification-methods-for-ai-chip-exports
5. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). https://github.com/Lucid-Computing/sovereignty-certificate-specification
6. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). https://arxiv.org/abs/2605.01930
7. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). https://www.cnas.org/publications/reports/secure-governable-chips
8. Verification Plan, R. Dean (2026). https://ai-2040.com/supplements/verification-plan
9. Get Involved in Verification, AI Futures Project (2026). https://ai-2040.com/supplements/verification-plan/get-involved
10. Verifying international AI deals: Plan A, the state-of-play, and what you can do to help, T. Milton et al. (2026). https://amodo.substack.com/p/verifying-international-ai-deals
11. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). https://amododesign.com/ai-verification/plan-a-sitrep/
12. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). https://amododesign.com/notes/2026-09-15-network-tap-inference-verification/
13. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). https://arxiv.org/abs/2511.02620
14. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). https://arxiv.org/abs/2608.23375
15. Physical Security and Tamper-Indicating Devices, R. G. Johnston & A. R. E. Garcia (1996). https://www.osti.gov/servlets/purl/459707
16. Tamper Detection for Safeguards and Treaty Monitoring: Fantasies, Realities, and Potentials, R. G. Johnston (2001). https://www.nonproliferation.org/wp-content/uploads/npr/81john.pdf
17. Tamper-Indicating Enclosures, A Current Survey, H. A. Smartt & Z. N. Gastelum (2015). https://www.osti.gov/servlets/purl/1256541
18. Secure Physical Enclosures from Covers with Tamper-Resistance, V. Immler et al. (2019). https://tches.iacr.org/index.php/TCHES/article/view/7334
19. Anti-Tamper Radio: System-Level Tamper Detection for Computing Systems, P. Staat et al. (2022). https://ieeexplore.ieee.org/document/9833631/
20. Anti-Tamper Radio Meets Reconfigurable Intelligent Surface for System-Level Tamper Detection, M. S. Tabar et al. (2025). https://arxiv.org/abs/2503.14279
21. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). https://arxiv.org/abs/2604.04712