# AI verification proposal

A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-08. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0018,M-0002&implementations=M-0018:I-0009

How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's readiness and open flaws. Readiness levels R0 to R4 describe one record's public evidence for its assessed use and are never combined. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and flaws) and https://trustbutveri.fyi/about/readiness/ (readiness levels).

## Filters

Filters apply to mechanisms only and describe the setting the proposal is for.

None set. Every mechanism on the map was available.

## Overview

One row per mechanism, read from its record. Open flaws: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees.

| Mechanism | Readiness | Prover | Attack testing | Hardware | Open flaws | Weights | Inputs and outputs | Training data |
| --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Chip location verification / Lucid sovereignty (location) certificates | R1 | Semi-trusted | Analysis | Existing features | 0 / 3 / 0 | unspecified | unspecified | unspecified |
| Deterministic and bit-exact inference | R3 | Adversarial | Analysis | None | 0 / 1 / 1 | depends | depends | not involved |

## Claims

No claims chosen.

## Mechanisms

### Chip location verification

A draft specification, hosted by Lucid Computing, for short-lived certificates that bound where a workload runs by timing signed exchanges with fixed anchors. ([Chip location verification](https://trustbutveri.fyi/mechanisms/chip-location-verification/))

- Assessment: selected implementation [Lucid sovereignty (location) certificates](https://trustbutveri.fyi/implementations/lucid-location-certificates/).
- Readiness: R1 Proposed, assessed for certifying the region where an attested workload ran at a given time.
- Claims in this proposal: none of them.
- Threat model: semi-trusted prover. Hardware: existing features. Prover cooperation: required. Attack testing: analysis. Category: Compute accounting & provenance.
- What the verifier sees: model weights unspecified; inputs and outputs unspecified; training data unspecified. This Explorer has no asset-specific exposure assessment for this implementation. Check its source and deployment assumptions.

### Deterministic and bit-exact inference

Making model inference reproducible bit for bit, so that a verifier's re-run must match the provider's output exactly rather than approximately. ([Deterministic and bit-exact inference](https://trustbutveri.fyi/mechanisms/deterministic-inference/))

- Assessment: mechanism family.
- Readiness: R3 In production, assessed for reproducing open-model inference from receipts in Gensyn's information-market service.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: none. Prover cooperation: required. Attack testing: analysis. Category: Cryptographic & computational.
- What the verifier sees: model weights depends; inputs and outputs depends; training data not involved. Exact replay needs the weights, configuration and replayed requests inside the recomputation environment. What the verifier sees depends on whether that environment keeps them confidential.


## Properties

**In production**

- Deterministic and bit-exact inference: R3 In production, assessed for reproducing open-model inference from receipts in Gensyn's information-market service

**Built for an adversarial prover**

- Deterministic and bit-exact inference

**No new hardware needed**

- Chip location verification
- Deterministic and bit-exact inference


## Attack testing

Published attempts to break a system, including those that found failures. Testing history does not establish that open flaws are resolved.

**Testing history**

- Chip location verification / Lucid sovereignty (location) certificates: Analysis
- Deterministic and bit-exact inference: Analysis


## Limits

**Open significant flaws**

- Physical attacks on the trusted hardware are out of scope (theoretical argument, in Lucid sovereignty (location) certificates; https://trustbutveri.fyi/implementations/lucid-location-certificates/#flaw-1) [1]. The specification places the hardware root of trust and the TEE in the trusted computing base. It assumes they resist software attacks, notes that the attacker may have physical access, and leaves sophisticated physical attacks, such as bus probing and side-channel analysis, as a residual risk. It says that future revisions may add requirements for physical tamper evidence.
- On-chip keys may be extractable (theoretical argument, in Lucid sovereignty (location) certificates; https://trustbutveri.fyi/implementations/lucid-location-certificates/#flaw-2) [1][5]. Tee and Happel argue that ping-based location protocols backed by keys stored on the chip can be compromised if an adversary with physical access extracts those keys. In this specification, the evidence chain rests on the hardware root of trust's signed quote, whose signing key must be protected by the hardware.
- General delay and landmark attacks apply (theoretical argument, in Lucid sovereignty (location) certificates; https://trustbutveri.fyi/implementations/lucid-location-certificates/#flaw-3) [1][6]. Attacks on delay-based location verification in general also apply. Brass and Aarne discuss adding delay, using faster paths such as dark fibre, and compromising landmarks. The specification counters anchor impersonation with a signed anchor directory. Against collusion it recommends anchors in diverse places run by several independent operators, and peer monitoring that temporarily removes anchors whose timings deviate.
- Cross-hardware replay relies on reverse-engineered, closed behaviour (open question, in Deterministic and bit-exact inference; https://trustbutveri.fyi/mechanisms/deterministic-inference/#flaw-2) [8][10]. Emulating one GPU's rounding on another requires reverse-engineering tensor-core arithmetic and modelling proprietary kernel choices. Hawkeye covers a subset of NVIDIA architectures and states that attention and other higher-level operations need further reverse engineering. For the bit-exact emulator, a proprietary Hopper kernel family is an open edge case.

**Family finding context**

- Context for Lucid sovereignty (location) certificates; applicability depends on the finding's scope. Extracting a chip's key lets another device answer for it (theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/#flaw-1) [5][6]. Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM.
- Context for Lucid sovereignty (location) certificates; applicability depends on the finding's scope. Added delay can shift an estimated position (demonstrated attack, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/#flaw-2) [6][7]. Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location.
- Context for Lucid sovereignty (location) certificates; applicability depends on the finding's scope. Faster-than-assumed network paths (theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/#flaw-3) [6][7]. Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often.
- Context for Lucid sovereignty (location) certificates; applicability depends on the finding's scope. Compromised landmarks can falsify measurements (theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/#flaw-4) [1][6][7]. A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators.

**Open minor flaws**

- Some kernels remain genuinely nondeterministic (open question, in Deterministic and bit-exact inference; https://trustbutveri.fyi/mechanisms/deterministic-inference/#flaw-1) [8]. The bit-exact work separates kernels that are deterministic but not batch-invariant from truly nondeterministic ones that use atomic functions. Some integer de-quantization kernels use atomic additions and remain nondeterministic, so exact replay needs backends that avoid them.

**Not yet demonstrated**

- Chip location verification: R1 Proposed, assessed for certifying the region where an attested workload ran at a given time


## Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open flaw or a dependency. Pointers, not recommendations: each brings its own readiness level and flaws, and none is claimed to close a flaw.

- **TEE remote attestation for AI workloads** (R3 In production, assessed for showing which software ran to a party that distrusts the operator holding the hardware)
  - Chip location verification depends on it.


## Dependencies

**Missing prerequisites**

- TEE remote attestation for AI workloads (R3 In production, assessed for showing which software ran to a party that distrusts the operator holding the hardware), needed by Chip location verification

**Blockers**

- Chip location verification: The specification is an unfinished draft with no public implementation or evaluation. (adversarial validation) [1][2]
- Chip location verification: It needs a globally distributed, trusted anchor fleet and an endorser to run the anchor directory. (access & governance) [1]
- Deterministic and bit-exact inference: Batch-invariant kernels cost throughput: in Thinking Machines' Qwen3-8B test, an improved deterministic build took 42 s against 26 s for vLLM's default, and SGLang reports an average 34.35% slowdown on its FlashInfer and FlashAttention 3 backends. (performance & compatibility) [9][11]
- Deterministic and bit-exact inference: Coverage is incomplete: the bit-exact emulator targets dense blocks on NVIDIA GPUs and excludes mixture-of-experts inference and training, and vLLM's batch-invariant mode is in beta, with open work on AMD hardware and speculative decoding. (performance & compatibility) [8][12][19]
- Deterministic and bit-exact inference: Amodo's status page for the AI 2040 verification plan rates a reproducible inference stack for that plan as 'not started'. (performance & compatibility) [20]
- Deterministic and bit-exact inference: Exact replay requires the prover to disclose weights, software versions, parallelism and batch sizes to whoever recomputes. (privacy & leakage) [8][18]


## What the verifier sees

- Model weights: shown by none; depends on the design for Deterministic and bit-exact inference; hidden by none; not involved in none; unspecified for Chip location verification.
- Inputs and outputs: shown by none; depends on the design for Deterministic and bit-exact inference; hidden by none; not involved in none; unspecified for Chip location verification.
- Training data: shown by none; depends on the design for none; hidden by none; not involved in Deterministic and bit-exact inference; unspecified for Chip location verification.

## Implementations

- Chip location verification: [Lucid sovereignty (location) certificates](https://trustbutveri.fyi/implementations/lucid-location-certificates/) (R1, standard)
- Deterministic and bit-exact inference: [Batch-invariant inference kernels (Thinking Machines)](https://trustbutveri.fyi/implementations/batch-invariant-inference-kernels/) (R2, open-source project); [Verde and RepOps (Gensyn)](https://trustbutveri.fyi/implementations/gensyn-verde-repops/) (R3, product); [Low-trust AI compute verification system overview](https://trustbutveri.fyi/implementations/low-trust-compute-verification-system-overview/) (R1, proposed architecture)

## Sources

1. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). https://github.com/Lucid-Computing/sovereignty-certificate-specification
2. Sovereignty Certificates Working Group (2026). https://sovcert.org/
3. Lucid Computing: Verifiable AI. Proven in hardware. (2026). https://lucidcomputing.ai/
4. Lucid Developer Platform documentation (2026). https://docs.lucidcomputing.ai/
5. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). https://arxiv.org/abs/2605.01930
6. Location Verification for AI Chips, A. Brass & O. Aarne (2024). https://www.iaps.ai/research/location-verification-for-ai-chips
7. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). https://www.iaps.ai/research/near-term-verification-methods-for-ai-chip-exports
8. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). https://arxiv.org/abs/2606.00279
9. Defeating Nondeterminism in LLM Inference, H. He & Thinking Machines Lab (2025). https://thinkingmachines.ai/blog/defeating-nondeterminism-in-llm-inference/
10. Hawkeye: Reproducing GPU-Level Non-Determinism, E. Badash et al. (2026). https://proceedings.mlsys.org/paper_files/paper/2026/hash/e217c271a57c365a246b0ad39e668ba8-Abstract-Conference.html
11. Towards Deterministic Inference in SGLang and Reproducible RL Training, The SGLang Team (2025). https://www.lmsys.org/blog/2025-09-22-sglang-deterministic/
12. Batch Invariance (vLLM documentation), vLLM project (2026). https://github.com/vllm-project/vllm/blob/main/docs/features/batch_invariance.md
13. gensyn-ai/ree: Gensyn Reproducible Execution Environment (GitHub repository), Gensyn (2026). https://github.com/gensyn-ai/ree
14. EigenCloud Brings Verifiable AI to Mass Market with EigenAI and EigenCompute Launches, EigenCloud (2025). https://www.eigenlabs.org/blog/eigencloud-brings-verifiable-ai-to-mass-market-with-eigenai-and-eigencompute-launches/
15. Building Delphi: Pricing, Settlement, and Agentic Trading, D. Jedamski (2026). https://www.gensyn.ai/blog/building-delphi-pricing-settlement-and-agentic-trading
16. Reproducible Execution Environment (REE) (Gensyn documentation), Gensyn (2026). https://docs.gensyn.ai/tech
17. What is Delphi? (Delphi documentation), Gensyn (2026). https://docs.delphi.fyi/
18. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). https://intelligence.org/wp-content/uploads/2026/06/A-system-overview-for-near-term-low-trust-AI-compute-verification.pdf
19. [Feature]: Batch Invariant Feature and Performance Optimization (vLLM issue #27433), vLLM project contributors (2025). https://github.com/vllm-project/vllm/issues/27433
20. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). https://amododesign.com/ai-verification/plan-a-sitrep/