# AI verification proposal

A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-08. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0010,M-0009,M-0012&tested=analysis

How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's readiness and open flaws. Readiness levels R0 to R4 describe one record's public evidence for its assessed use and are never combined. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and flaws) and https://trustbutveri.fyi/about/readiness/ (readiness levels).

## Filters

Filters apply to mechanisms only and describe the setting the proposal is for.

- **Attack testing: Published analysis.** Keeps mechanisms whose strongest published attack testing is at least this. The strongest published attempt to break the mechanism for its verification use: a security analysis, red-teaming by its developers or collaborators, or a red team independent of them.

24 of 25 mechanisms on the map pass these filters.

## Overview

One row per mechanism, read from its record. Open flaws: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees.

| Mechanism | Readiness | Prover | Attack testing | Hardware | Open flaws | Weights | Inputs and outputs | Training data |
| --- | --- | --- | --- | --- | --- | --- | --- | --- |
| On-chip telemetry from timing, memory and performance counters | R2 | Semi-trusted | Red-teamed | Existing features | 1 / 3 / 1 | depends | depends | depends |
| Hardware-enabled guarantees (flexHEG) and guarantee processors | R1 | Adversarial | Analysis | New chip design | 0 / 6 / 0 | hidden | hidden | hidden |
| Model identity attestation | R3 | Semi-trusted | Independent red-team | Existing features | 1 / 2 / 0 | depends | depends | not involved |

## Claims

No claims chosen.

## Mechanisms

### On-chip telemetry from timing, memory and performance counters

Uses timing, memory-residency and performance-counter signals measured on AI accelerators as evidence about which workloads they are running. ([On-chip telemetry from timing, memory and performance counters](https://trustbutveri.fyi/mechanisms/on-chip-telemetry/))

- Assessment: mechanism family.
- Readiness: R2 Demonstrated, assessed for workload evidence from GPU counters and timing, assuming authentic measurements.
- Claims in this proposal: none of them.
- Threat model: semi-trusted prover. Hardware: existing features. Prover cooperation: partial. Attack testing: red-teamed. Category: On-chip & hardware-enabled.
- What the verifier sees: model weights depends; inputs and outputs depends; training data depends. Counters do not read weights or data, but richer counters can leak secrets through side channels.

### Hardware-enabled guarantees (flexHEG) and guarantee processors

Proposed chip add-ons, a guarantee processor inside a tamper-protected enclosure, that would check and enforce agreed rules on how AI accelerators are used. ([Hardware-enabled guarantees (flexHEG) and guarantee processors](https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/))

- Assessment: mechanism family.
- Readiness: R1 Proposed, assessed for checking and enforcing training-compute limits on chips, against adversaries up to states.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: new chip design. Prover cooperation: required. Attack testing: analysis. Category: On-chip & hardware-enabled.
- What the verifier sees: model weights hidden; inputs and outputs hidden; training data hidden. The guarantee processor sees the chip's traffic inside a sealed enclosure and reports only whether rules were kept.

### Model identity attestation

Establishes that responses come from a specific, committed set of model weights, using enclave measurements or recomputation of sampled outputs. ([Model identity attestation](https://trustbutveri.fyi/mechanisms/model-identity-attestation/))

- Assessment: mechanism family.
- Readiness: R3 In production, assessed for showing users that a service runs the declared model weights.
- Claims in this proposal: none of them.
- Threat model: semi-trusted prover. Hardware: existing features. Prover cooperation: required. Attack testing: independent red-team. Category: Cryptographic & computational.
- What the verifier sees: model weights depends; inputs and outputs depends; training data not involved. The enclave route shows only hashes; the recomputation route gives the verifier the weights and the sampled requests and responses.


## Properties

**In production**

- Model identity attestation: R3 In production, assessed for showing users that a service runs the declared model weights

**Built for an adversarial prover**

- Hardware-enabled guarantees (flexHEG) and guarantee processors

**No new hardware needed**

- On-chip telemetry from timing, memory and performance counters
- Model identity attestation

**Flaws since mitigated**

- Launch-state attestation does not by itself cover weights loaded later (in Model identity attestation) [4][12]


## Attack testing

Published attempts to break a system, including those that found failures. Testing history does not establish that open flaws are resolved.

**Testing history**

- On-chip telemetry from timing, memory and performance counters: Red-teamed
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Analysis
- Model identity attestation: Independent red-team


## Limits

**Open critical flaws**

- Software-read telemetry can be forged by the operator (theoretical argument, in On-chip telemetry from timing, memory and performance counters; https://trustbutveri.fyi/mechanisms/on-chip-telemetry/#flaw-1) [1][3]. NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized.

  Related mechanism: Hardware-enabled guarantees (flexHEG) and guarantee processors (R1, in the proposal). A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing.
- Underlying attestation can be forged or relayed (demonstrated attack, in Model identity attestation; https://trustbutveri.fyi/mechanisms/model-identity-attestation/#flaw-1) [13][15][19][21][22][23]. Inherited finding. Critical for the enclave route against an operator with physical access to affected hardware, or control of an unpatched SEV-SNP hypervisor. It does not apply to the recomputation route. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary. The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. Related finding: https://trustbutveri.fyi/mechanisms/tee-remote-attestation/#flaw-1.

  Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

  Related mechanism: Hardware-enabled guarantees (flexHEG) and guarantee processors (R1, in the proposal). A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.

**Open significant flaws**

- Adversarially disguised fine-tuning partly evades classification (demonstrated attack, in On-chip telemetry from timing, memory and performance counters; https://trustbutveri.fyi/mechanisms/on-chip-telemetry/#flaw-2) [3]. Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware.
- Timing challenges do not identify the individual chip (theoretical argument, in On-chip telemetry from timing, memory and performance counters; https://trustbutveri.fyi/mechanisms/on-chip-telemetry/#flaw-3) [1]. GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use.
- Counters leak information about protected workloads (theoretical argument, in On-chip telemetry from timing, memory and performance counters; https://trustbutveri.fyi/mechanisms/on-chip-telemetry/#flaw-4) [4][5]. Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality.
- State attackers can likely defeat current secure enclosures (theoretical argument, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-1) [7][9]. The flexHEG authors write that "nation-state attackers can likely compromise the best current secure enclosures", and that the marginal cost of circumvention per device is hard to estimate. RAND similarly judges that anti-tamper measures "would not be insurmountable for a determined and well-resourced adversary", although they raise costs and can reveal tampering.
- Firmware-only retrofits rely on Secure Boot, which fault injection can bypass (theoretical argument, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-2) [7]. Part II notes that the most common attack on Secure Boot replaces the firmware and applies a voltage glitch while the signature is being checked. It also notes that sophisticated actors may use microprobing or laser voltage probing to read key registers.
- Many important rules cannot be checked on-chip (theoretical argument, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-3) [6][8]. Malicious intent "is not a technical property observable on-chip", and misuse depends on what is done with a computation's results. A guarantee processor cannot easily tell whether a network is the whole system or one expert in a mixture-of-experts system. Part III judges that a fully local ruleset "may not be entirely feasible" for the same reason.
- FLOP accounting can be laundered through external data (theoretical argument, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-4) [7]. Results of earlier or parallel workloads could be hidden in the "external data" fed to a device, which would falsify the total FLOP count unless the inputs are explained or time delays are imposed.
- Supply-chain diversion and hidden backdoors (open question, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-5) [7][8]. Components could be diverted before a guarantee processor is added, and backdoors could be introduced during design or manufacturing. Open-source designs and physical scans of randomly selected chips are proposed as countermeasures. Part III proposes international oversight of production and extensive testing of a random sample of finished devices.

  Related mechanism: Chip registries and manufacturing records (R1, not in the proposal). Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors.
- Coverage stops at flexHEG-equipped chips (open question, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-6) [6][8]. Motivated actors will always be able to use some compute that is not flexHEG-equipped. Recalling existing consumer GPUs would likely be impractical, and reaching perfect coverage, or conclusively proving that no secret government data centres exist, would be "practically quite difficult".

  Related mechanism: Chip registries and manufacturing records (R1, not in the proposal). Accounts for which chips exist and who holds them.

  Related mechanism: Remote detection of data centres (R1, not in the proposal). Looks for undeclared facilities that hold other chips.
- For private models, a user can confirm consistency but not content (open question, in Model identity attestation; https://trustbutveri.fyi/mechanisms/model-identity-attestation/#flaw-3) [12][24]. When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy.
- Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel (demonstrated attack, in Model identity attestation; https://trustbutveri.fyi/mechanisms/model-identity-attestation/#flaw-4) [14][20]. The recomputation variant assumes that every input, output and seed is logged correctly, and that the attacker can neither predict nor manipulate which messages are sampled for verification. Legitimate nondeterminism concentrates at a few token positions, and slow leaks within the tolerated slack remain possible. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token, reducing the exfiltration slowdown from 146–254 times under benign prompts to 60–118 times. The attack targets the exfiltration bound, not the check that outputs match the declared model.

  Related mechanism: Network taps and certifiers (R1, not in the proposal). Taps are proposed to copy and hash traffic on the monitored links, reducing reliance on the prover's own log. This still depends on the monitored boundary and trusted capture.

  Related mechanism: Deterministic and bit-exact inference (R3, not in the proposal). Bit-exact inference would remove the numerical tolerance that leaves this channel.

**Open minor flaws**

- No quantified error rates or formal thresholds for timing primitives (open question, in On-chip telemetry from timing, memory and performance counters; https://trustbutveri.fyi/mechanisms/on-chip-telemetry/#flaw-5) [1]. Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work.

**Not yet demonstrated**

- Hardware-enabled guarantees (flexHEG) and guarantee processors: R1 Proposed, assessed for checking and enforcing training-compute limits on chips, against adversaries up to states

**Need new chip designs**

- Hardware-enabled guarantees (flexHEG) and guarantee processors


## Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open flaw or a dependency. Pointers, not recommendations: each brings its own readiness level and flaws, and none is claimed to close a flaw.

- **Deterministic and bit-exact inference** (R3 In production, assessed for reproducing open-model inference from receipts in Gensyn's information-market service)
  - Bears on the open significant flaw "Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel" in Model identity attestation. Bit-exact inference would remove the numerical tolerance that leaves this channel.
  - Model identity attestation waits on it: Numerical nondeterminism limits how tightly recomputation can pin down the model and sampling.
- **Chip registries and manufacturing records** (R1 Proposed, assessed for a checkable record of which chips were made and who declared owning them)
  - Bears on the open significant flaw "Supply-chain diversion and hidden backdoors" in Hardware-enabled guarantees (flexHEG) and guarantee processors. Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors.
  - Bears on the open significant flaw "Coverage stops at flexHEG-equipped chips" in Hardware-enabled guarantees (flexHEG) and guarantee processors. Accounts for which chips exist and who holds them.
  - Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it: Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities.
- **Network taps and certifiers** (R1 Proposed, assessed for committing a complete record of cluster traffic, so declared inference can be checked)
  - Bears on the open significant flaw "Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel" in Model identity attestation. Taps are proposed to copy and hash traffic on the monitored links, reducing reliance on the prover's own log. This still depends on the monitored boundary and trusted capture.
- **Remote detection of data centres** (R1 Proposed, assessed for finding undeclared data centres above an agreed compute threshold)
  - Bears on the open significant flaw "Coverage stops at flexHEG-equipped chips" in Hardware-enabled guarantees (flexHEG) and guarantee processors. Looks for undeclared facilities that hold other chips.
- **TEE remote attestation for AI workloads** (R3 In production, assessed for showing which software ran to a party that distrusts the operator holding the hardware)
  - Model identity attestation waits on it: Attestation that resists physical attackers, for the enclave variant.
  - On-chip telemetry from timing, memory and performance counters depends on it.
  - Hardware-enabled guarantees (flexHEG) and guarantee processors depends on it.
- **Tamper evidence for verifier devices** (R2 Demonstrated, assessed for detecting probing of proposed verifier hardware, using server and electronics prototypes as evidence)
  - Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it: State-level attackers who hold the hardware can likely compromise the best current secure enclosures.


## Dependencies

**Missing prerequisites**

- TEE remote attestation for AI workloads (R3 In production, assessed for showing which software ran to a party that distrusts the operator holding the hardware), needed by On-chip telemetry from timing, memory and performance counters and Hardware-enabled guarantees (flexHEG) and guarantee processors
- Chip registries and manufacturing records (R1 Proposed, assessed for a checkable record of which chips were made and who declared owning them), needed by Hardware-enabled guarantees (flexHEG) and guarantee processors

**Shared foundations**

- TEE remote attestation for AI workloads, relied on by On-chip telemetry from timing, memory and performance counters, Hardware-enabled guarantees (flexHEG) and guarantee processors and Model identity attestation

**Blockers**

- On-chip telemetry from timing, memory and performance counters: Shipping accelerators need a tamper-resistant, authenticated telemetry path. (hardware trust; waits on Hardware-enabled guarantees (flexHEG) and guarantee processors) [2][3]
- On-chip telemetry from timing, memory and performance counters: NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. (privacy & leakage) [4][5]
- On-chip telemetry from timing, memory and performance counters: Continuous challenge puzzles cost power and throughput on production workloads. (performance & compatibility) [1]
- On-chip telemetry from timing, memory and performance counters: Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. (adversarial validation) [3]
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Integrated flexHEG needs substantial help from the accelerator manufacturer, and the authors estimate 3.7–7.9 years, from when the manufacturer starts work, for such hardware to displace other accelerators in frontier development. (access & governance) [7]
- Hardware-enabled guarantees (flexHEG) and guarantee processors: State-level attackers who hold the hardware can likely compromise the best current secure enclosures. (hardware trust; waits on Tamper evidence for verifier devices) [7][9]
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Rival states would need to trust the design and manufacture of guarantee processors and enclosures, for example through open design, redundant processors from each side or oversight of production. (hardware trust) [6][8]
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Restricting future rule updates would need a formal language for rules, which the authors judge most likely infeasible for early flexHEG versions. (protocol soundness) [6]
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities. (coverage & hidden compute; waits on Chip registries and manufacturing records) [8]
- Model identity attestation: Attestation that resists physical attackers, for the enclave variant. (hardware trust; waits on TEE remote attestation for AI workloads) [19]
- Model identity attestation: Numerical nondeterminism limits how tightly recomputation can pin down the model and sampling. (protocol soundness; waits on Deterministic and bit-exact inference) [14]
- Model identity attestation: The recomputation variant needs the verifier to hold the declared weights. (access & governance) [14]


## What the verifier sees

- Model weights: shown by none; depends on the design for On-chip telemetry from timing, memory and performance counters and Model identity attestation; hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors; not involved in none; unspecified for none.
- Inputs and outputs: shown by none; depends on the design for On-chip telemetry from timing, memory and performance counters and Model identity attestation; hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors; not involved in none; unspecified for none.
- Training data: shown by none; depends on the design for On-chip telemetry from timing, memory and performance counters; hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors; not involved in Model identity attestation; unspecified for none.

## Implementations

- On-chip telemetry from timing, memory and performance counters: none on the map
- Hardware-enabled guarantees (flexHEG) and guarantee processors: none on the map
- Model identity attestation: [Attestable Audits](https://trustbutveri.fyi/implementations/attestable-audits/) (R2, research prototype); [PAL*M](https://trustbutveri.fyi/implementations/palm/) (R2, research prototype); [Tinfoil model identity (Modelwrap)](https://trustbutveri.fyi/implementations/tinfoil-model-identity/) (R3, product)

## Sources

1. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). https://arxiv.org/abs/2602.09369
2. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). https://openreview.net/forum?id=uc79kOv0MV
3. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). https://arxiv.org/abs/2606.19262
4. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). https://techgov.intelligence.org/blog/on-tees-for-privacy-preserving-monitoring-in-ai-governance
5. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). https://docs.nvidia.com/nvidia-secure-ai-with-blackwell-and-hopper-gpus-whitepaper.pdf
6. Flexible Hardware-Enabled Guarantees for AI Compute, J. Petrie et al. (2025). https://arxiv.org/abs/2506.15093
7. Technical Options for Flexible Hardware-Enabled Guarantees, J. Petrie & O. Aarne (2025). https://arxiv.org/abs/2506.03409
8. International Security Applications of Flexible Hardware-Enabled Guarantees, O. Aarne & J. Petrie (2025). https://arxiv.org/abs/2506.15100
9. Hardware-Enabled Governance Mechanisms: Developing Technical Solutions to Exempt Items Otherwise Classified Under Export Control Classification Numbers 3A090 and 4A090, G. Kulp et al. (2024). https://www.rand.org/pubs/working_papers/WRA3056-1.html
10. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). https://www.cnas.org/publications/reports/secure-governable-chips
11. Hardware-Enabled Mechanisms for Verifying Responsible AI Development, A. O'Gara et al. (2025). https://arxiv.org/abs/2505.03742
12. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). https://tinfoil.sh/blog/2026-02-03-proving-model-identity
13. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). https://arxiv.org/abs/2601.16199
14. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). https://arxiv.org/abs/2511.02620
15. A primer on secure enclaves, Tinfoil (2026). https://docs.tinfoil.sh/verification/secure-enclave-primer
16. Backend infrastructure, Tinfoil (2026). https://docs.tinfoil.sh/verification/attestation-architecture
17. How verification works in Tinfoil, Tinfoil (2026). https://docs.tinfoil.sh/verification/verification-in-tinfoil
18. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). https://github.com/tinfoilsh/modelwrap
19. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). https://tee.fail/
20. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). https://arxiv.org/abs/2608.23375
21. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). https://batteringram.eu/
22. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). https://rmpocalypse.github.io/
23. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). https://www.amd.com/en/resources/product-security/bulletin/amd-sb-3020.html
24. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). https://arxiv.org/abs/2506.23706