# AI verification proposal

A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-08. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0012,M-0009,M-0013

How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's readiness and open flaws. Readiness levels R0 to R4 describe one record's public evidence for its assessed use and are never combined. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and flaws) and https://trustbutveri.fyi/about/readiness/ (readiness levels).

## Filters

Filters apply to mechanisms only and describe the setting the proposal is for.

None set. Every mechanism on the map was available.

## Overview

One row per mechanism, read from its record. Open flaws: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees.

| Mechanism | Readiness | Prover | Attack testing | Hardware | Open flaws | Weights | Inputs and outputs | Training data |
| --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Model identity attestation | R3 | Semi-trusted | Independent red-team | Existing features | 1 / 2 / 0 | depends | depends | not involved |
| Hardware-enabled guarantees (flexHEG) and guarantee processors | R1 | Adversarial | Analysis | New chip design | 0 / 6 / 0 | hidden | hidden | hidden |
| Network taps and certifiers | R1 | Adversarial | Analysis | Retrofit device | 0 / 5 / 0 | depends | depends | depends |

## Claims

No claims chosen.

## Mechanisms

### Model identity attestation

Establishes that responses come from a specific, committed set of model weights, using enclave measurements or recomputation of sampled outputs. ([Model identity attestation](https://trustbutveri.fyi/mechanisms/model-identity-attestation/))

- Assessment: mechanism family.
- Readiness: R3 In production, assessed for showing users that a service runs the declared model weights.
- Claims in this proposal: none of them.
- Threat model: semi-trusted prover. Hardware: existing features. Prover cooperation: required. Attack testing: independent red-team. Category: Cryptographic & computational.
- What the verifier sees: model weights depends; inputs and outputs depends; training data not involved. The enclave route shows only hashes; the recomputation route gives the verifier the weights and the sampled requests and responses.

### Hardware-enabled guarantees (flexHEG) and guarantee processors

Proposed chip add-ons, a guarantee processor inside a tamper-protected enclosure, that would check and enforce agreed rules on how AI accelerators are used. ([Hardware-enabled guarantees (flexHEG) and guarantee processors](https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/))

- Assessment: mechanism family.
- Readiness: R1 Proposed, assessed for checking and enforcing training-compute limits on chips, against adversaries up to states.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: new chip design. Prover cooperation: required. Attack testing: analysis. Category: On-chip & hardware-enabled.
- What the verifier sees: model weights hidden; inputs and outputs hidden; training data hidden. The guarantee processor sees the chip's traffic inside a sealed enclosure and reports only whether rules were kept.

### Network taps and certifiers

Devices on a cluster's network links that copy and hash all traffic, so a verifier can later check sampled records against declared work. ([Network taps and certifiers](https://trustbutveri.fyi/mechanisms/network-taps-and-certifiers/))

- Assessment: mechanism family.
- Readiness: R1 Proposed, assessed for committing a complete record of cluster traffic, so declared inference can be checked.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: retrofit device. Prover cooperation: required. Attack testing: analysis. Category: Off-chip devices & sensors.
- What the verifier sees: model weights depends; inputs and outputs depends; training data depends. Only hashes leave the site; records picked for a challenge are opened for replay at a verification facility.


## Properties

**In production**

- Model identity attestation: R3 In production, assessed for showing users that a service runs the declared model weights

**Built for an adversarial prover**

- Hardware-enabled guarantees (flexHEG) and guarantee processors
- Network taps and certifiers

**No new hardware needed**

- Model identity attestation

**Flaws since mitigated**

- Launch-state attestation does not by itself cover weights loaded later (in Model identity attestation) [1][13]
- Verifier dictionary attacks on hashes (in Network taps and certifiers) [21]


## Attack testing

Published attempts to break a system, including those that found failures. Testing history does not establish that open flaws are resolved.

**Testing history**

- Model identity attestation: Independent red-team
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Analysis
- Network taps and certifiers: Analysis


## Limits

**Open critical flaws**

- Underlying attestation can be forged or relayed (demonstrated attack, in Model identity attestation; https://trustbutveri.fyi/mechanisms/model-identity-attestation/#flaw-1) [2][4][8][10][11][12]. Inherited finding. Critical for the enclave route against an operator with physical access to affected hardware, or control of an unpatched SEV-SNP hypervisor. It does not apply to the recomputation route. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary. The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. Related finding: https://trustbutveri.fyi/mechanisms/tee-remote-attestation/#flaw-1.

  Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

  Related mechanism: Hardware-enabled guarantees (flexHEG) and guarantee processors (R1, in the proposal). A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.

**Open significant flaws**

- For private models, a user can confirm consistency but not content (open question, in Model identity attestation; https://trustbutveri.fyi/mechanisms/model-identity-attestation/#flaw-3) [1][14]. When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy.
- Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel (demonstrated attack, in Model identity attestation; https://trustbutveri.fyi/mechanisms/model-identity-attestation/#flaw-4) [3][9]. The recomputation variant assumes that every input, output and seed is logged correctly, and that the attacker can neither predict nor manipulate which messages are sampled for verification. Legitimate nondeterminism concentrates at a few token positions, and slow leaks within the tolerated slack remain possible. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token, reducing the exfiltration slowdown from 146–254 times under benign prompts to 60–118 times. The attack targets the exfiltration bound, not the check that outputs match the declared model.

  Related mechanism: Network taps and certifiers (R1, in the proposal). Taps are proposed to copy and hash traffic on the monitored links, reducing reliance on the prover's own log. This still depends on the monitored boundary and trusted capture.

  Related mechanism: Deterministic and bit-exact inference (R3, not in the proposal). Bit-exact inference would remove the numerical tolerance that leaves this channel.
- State attackers can likely defeat current secure enclosures (theoretical argument, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-1) [16][18]. The flexHEG authors write that "nation-state attackers can likely compromise the best current secure enclosures", and that the marginal cost of circumvention per device is hard to estimate. RAND similarly judges that anti-tamper measures "would not be insurmountable for a determined and well-resourced adversary", although they raise costs and can reveal tampering.
- Firmware-only retrofits rely on Secure Boot, which fault injection can bypass (theoretical argument, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-2) [16]. Part II notes that the most common attack on Secure Boot replaces the firmware and applies a voltage glitch while the signature is being checked. It also notes that sophisticated actors may use microprobing or laser voltage probing to read key registers.
- Many important rules cannot be checked on-chip (theoretical argument, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-3) [15][17]. Malicious intent "is not a technical property observable on-chip", and misuse depends on what is done with a computation's results. A guarantee processor cannot easily tell whether a network is the whole system or one expert in a mixture-of-experts system. Part III judges that a fully local ruleset "may not be entirely feasible" for the same reason.
- FLOP accounting can be laundered through external data (theoretical argument, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-4) [16]. Results of earlier or parallel workloads could be hidden in the "external data" fed to a device, which would falsify the total FLOP count unless the inputs are explained or time delays are imposed.
- Supply-chain diversion and hidden backdoors (open question, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-5) [16][17]. Components could be diverted before a guarantee processor is added, and backdoors could be introduced during design or manufacturing. Open-source designs and physical scans of randomly selected chips are proposed as countermeasures. Part III proposes international oversight of production and extensive testing of a random sample of finished devices.

  Related mechanism: Chip registries and manufacturing records (R1, not in the proposal). Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors.
- Coverage stops at flexHEG-equipped chips (open question, in Hardware-enabled guarantees (flexHEG) and guarantee processors; https://trustbutveri.fyi/mechanisms/flexheg-guarantee-processors/#flaw-6) [15][17]. Motivated actors will always be able to use some compute that is not flexHEG-equipped. Recalling existing consumer GPUs would likely be impractical, and reaching perfect coverage, or conclusively proving that no secret government data centres exist, would be "practically quite difficult".

  Related mechanism: Chip registries and manufacturing records (R1, not in the proposal). Accounts for which chips exist and who holds them.

  Related mechanism: Remote detection of data centres (R1, not in the proposal). Looks for undeclared facilities that hold other chips.
- Output nondeterminism leaves covert capacity (theoretical argument, in Network taps and certifiers; https://trustbutveri.fyi/mechanisms/network-taps-and-certifiers/#flaw-1) [9][21]. Hashing cannot remove information hidden in the outputs themselves. The Secure Gateway Device paper estimates that about 0.1 bit per token remains even with seed-synchronized replay checks. For a 200k-GPU inference cluster at full load (2,000 tokens per GPU per second), that is about 40 Mbit/s of covert egress, enough to move a 1 TB model in under three days. The paper names this the core remaining challenge and points to deterministic replay or active scrubbing of hardware-induced entropy. An independent study found that an adversary who chooses the prompts roughly doubles the bits leaked per token under Gumbel-based inference verification; see Bounding unexplained information in outputs.

  Related mechanism: Deterministic and bit-exact inference (R3, not in the proposal). Deterministic replay is one of the two remedies the flaw's source names.

  Related mechanism: Bounding unexplained information in outputs (R2, not in the proposal). Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict.
- Some links cannot be passively tapped (open question, in Network taps and certifiers; https://trustbutveri.fyi/mechanisms/network-taps-and-certifiers/#flaw-2) [22][29]. Cankaya notes that copper-connected scale-up domains (for example NVL72 racks and TPU v7 cubes) are much harder to tap than fibre, and that optical budgets make passive taps impractical on 400GBASE-SR8 multimode links. Amodo found no taps advertised for 53 GBaud links as of May 2026.
- Encrypted fabrics hide plaintext from both parties (open question, in Network taps and certifiers; https://trustbutveri.fyi/mechanisms/network-taps-and-certifiers/#flaw-3) [22]. Cankaya notes that with TEE-protected sessions whose keys are ephemeral and managed inside the TEE, neither the operator nor the manufacturer can recover session keys after the session, so tapped traffic could not be opened for recomputation. For other encrypted fabrics, the operator can retain keys.
- Residual side channels in simple passive setups (theoretical argument, in Network taps and certifiers; https://trustbutveri.fyi/mechanisms/network-taps-and-certifiers/#flaw-4) [25]. Amodo's analysis of its own tapped prototype lists unvalidated header fields, timing of permitted traffic and variation in response formatting as residual channels, and concludes that the passive tap must be replaced by an active one.
- Completeness rests on physical monitoring left out of scope (open question, in Network taps and certifiers; https://trustbutveri.fyi/mechanisms/network-taps-and-certifiers/#flaw-5) [21]. The Secure Gateway Device paper assumes the facility is physically monitored, and states that the whole architecture depends on the device being the only communication channel. It names radio emanation, power-line signalling and thermal channels as covert channels beyond that scope.

  Related mechanism: Side-channel suppression for isolated facilities (R1, not in the proposal). Addresses the radio, power-line and thermal channels that network-level designs leave out.

**Not yet demonstrated**

- Hardware-enabled guarantees (flexHEG) and guarantee processors: R1 Proposed, assessed for checking and enforcing training-compute limits on chips, against adversaries up to states
- Network taps and certifiers: R1 Proposed, assessed for committing a complete record of cluster traffic, so declared inference can be checked

**Need new chip designs**

- Hardware-enabled guarantees (flexHEG) and guarantee processors


## Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open flaw or a dependency. Pointers, not recommendations: each brings its own readiness level and flaws, and none is claimed to close a flaw.

- **Deterministic and bit-exact inference** (R3 In production, assessed for reproducing open-model inference from receipts in Gensyn's information-market service)
  - Bears on the open significant flaw "Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel" in Model identity attestation. Bit-exact inference would remove the numerical tolerance that leaves this channel.
  - Bears on the open significant flaw "Output nondeterminism leaves covert capacity" in Network taps and certifiers. Deterministic replay is one of the two remedies the flaw's source names.
  - Model identity attestation waits on it: Numerical nondeterminism limits how tightly recomputation can pin down the model and sampling.
  - Network taps and certifiers waits on it: Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove.
- **Bounding unexplained information in outputs** (R2 Demonstrated, assessed for bounding how much hidden information can leave in checked inference outputs)
  - Bears on the open significant flaw "Output nondeterminism leaves covert capacity" in Network taps and certifiers. Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict.
- **Chip registries and manufacturing records** (R1 Proposed, assessed for a checkable record of which chips were made and who declared owning them)
  - Bears on the open significant flaw "Supply-chain diversion and hidden backdoors" in Hardware-enabled guarantees (flexHEG) and guarantee processors. Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors.
  - Bears on the open significant flaw "Coverage stops at flexHEG-equipped chips" in Hardware-enabled guarantees (flexHEG) and guarantee processors. Accounts for which chips exist and who holds them.
  - Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it: Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities.
- **Remote detection of data centres** (R1 Proposed, assessed for finding undeclared data centres above an agreed compute threshold)
  - Bears on the open significant flaw "Coverage stops at flexHEG-equipped chips" in Hardware-enabled guarantees (flexHEG) and guarantee processors. Looks for undeclared facilities that hold other chips.
- **Side-channel suppression for isolated facilities** (R1 Proposed, assessed for bounding physical covert channels out of a verified enclosure)
  - Bears on the open significant flaw "Completeness rests on physical monitoring left out of scope" in Network taps and certifiers. Addresses the radio, power-line and thermal channels that network-level designs leave out.
  - Network taps and certifiers waits on it: Radio, power-line and thermal channels are not addressed by network-level designs.
- **TEE remote attestation for AI workloads** (R3 In production, assessed for showing which software ran to a party that distrusts the operator holding the hardware)
  - Model identity attestation waits on it: Attestation that resists physical attackers, for the enclave variant.
  - Hardware-enabled guarantees (flexHEG) and guarantee processors depends on it.
- **Tamper evidence for verifier devices** (R2 Demonstrated, assessed for detecting probing of proposed verifier hardware, using server and electronics prototypes as evidence)
  - Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it: State-level attackers who hold the hardware can likely compromise the best current secure enclosures.
  - Network taps and certifiers waits on it: Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them.
- **Sampled inference recomputation** (R3 In production, assessed for checking untrusted workers' activations against the declared model, prompt and precision)
  - Network taps and certifiers depends on it.


## Dependencies

**Missing prerequisites**

- TEE remote attestation for AI workloads (R3 In production, assessed for showing which software ran to a party that distrusts the operator holding the hardware), needed by Hardware-enabled guarantees (flexHEG) and guarantee processors
- Chip registries and manufacturing records (R1 Proposed, assessed for a checkable record of which chips were made and who declared owning them), needed by Hardware-enabled guarantees (flexHEG) and guarantee processors
- Sampled inference recomputation (R3 In production, assessed for checking untrusted workers' activations against the declared model, prompt and precision), needed by Network taps and certifiers
- Deterministic and bit-exact inference (R3 In production, assessed for reproducing open-model inference from receipts in Gensyn's information-market service), needed by Network taps and certifiers
- Tamper evidence for verifier devices (R2 Demonstrated, assessed for detecting probing of proposed verifier hardware, using server and electronics prototypes as evidence), needed by Network taps and certifiers
- Side-channel suppression for isolated facilities (R1 Proposed, assessed for bounding physical covert channels out of a verified enclosure), needed by Network taps and certifiers

**Shared foundations**

- TEE remote attestation for AI workloads, relied on by Model identity attestation and Hardware-enabled guarantees (flexHEG) and guarantee processors
- Deterministic and bit-exact inference, relied on by Model identity attestation and Network taps and certifiers
- Tamper evidence for verifier devices, relied on by Hardware-enabled guarantees (flexHEG) and guarantee processors and Network taps and certifiers

**Blockers**

- Model identity attestation: Attestation that resists physical attackers, for the enclave variant. (hardware trust; waits on TEE remote attestation for AI workloads) [8]
- Model identity attestation: Numerical nondeterminism limits how tightly recomputation can pin down the model and sampling. (protocol soundness; waits on Deterministic and bit-exact inference) [3]
- Model identity attestation: The recomputation variant needs the verifier to hold the declared weights. (access & governance) [3]
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Integrated flexHEG needs substantial help from the accelerator manufacturer, and the authors estimate 3.7–7.9 years, from when the manufacturer starts work, for such hardware to displace other accelerators in frontier development. (access & governance) [16]
- Hardware-enabled guarantees (flexHEG) and guarantee processors: State-level attackers who hold the hardware can likely compromise the best current secure enclosures. (hardware trust; waits on Tamper evidence for verifier devices) [16][18]
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Rival states would need to trust the design and manufacture of guarantee processors and enclosures, for example through open design, redundant processors from each side or oversight of production. (hardware trust) [15][17]
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Restricting future rule updates would need a formal language for rules, which the authors judge most likely infeasible for early flexHEG versions. (protocol soundness) [15]
- Hardware-enabled guarantees (flexHEG) and guarantee processors: Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities. (coverage & hidden compute; waits on Chip registries and manufacturing records) [17]
- Network taps and certifiers: No complete verification tap has been demonstrated at production frontend link rates, and on the tested CPU no hash algorithm reached line rate with minimum-size frames. (performance & compatibility) [29][30]
- Network taps and certifiers: Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove. (evidence binding; waits on Deterministic and bit-exact inference) [21]
- Network taps and certifiers: Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them. (hardware trust; waits on Tamper evidence for verifier devices) [21][23]
- Network taps and certifiers: Radio, power-line and thermal channels are not addressed by network-level designs. (coverage & hidden compute; waits on Side-channel suppression for isolated facilities) [21]
- Network taps and certifiers: Red-teaming by specialists is called for but has not been reported. (adversarial validation) [21]


## What the verifier sees

- Model weights: shown by none; depends on the design for Model identity attestation and Network taps and certifiers; hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors; not involved in none; unspecified for none.
- Inputs and outputs: shown by none; depends on the design for Model identity attestation and Network taps and certifiers; hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors; not involved in none; unspecified for none.
- Training data: shown by none; depends on the design for Network taps and certifiers; hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors; not involved in Model identity attestation; unspecified for none.

## Implementations

- Model identity attestation: [Attestable Audits](https://trustbutveri.fyi/implementations/attestable-audits/) (R2, research prototype); [PAL*M](https://trustbutveri.fyi/implementations/palm/) (R2, research prototype); [Tinfoil model identity (Modelwrap)](https://trustbutveri.fyi/implementations/tinfoil-model-identity/) (R3, product)
- Hardware-enabled guarantees (flexHEG) and guarantee processors: none on the map
- Network taps and certifiers: [AI 2040 inference-only verification stack](https://trustbutveri.fyi/implementations/ai-2040-inference-only-verification-plan/) (R1, proposed architecture); [Low-trust AI compute verification system overview](https://trustbutveri.fyi/implementations/low-trust-compute-verification-system-overview/) (R1, proposed architecture); [SASH confidential network logger](https://trustbutveri.fyi/implementations/sash-confidential-network-logger/) (R1, research prototype)

## Sources

1. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). https://tinfoil.sh/blog/2026-02-03-proving-model-identity
2. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). https://arxiv.org/abs/2601.16199
3. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). https://arxiv.org/abs/2511.02620
4. A primer on secure enclaves, Tinfoil (2026). https://docs.tinfoil.sh/verification/secure-enclave-primer
5. Backend infrastructure, Tinfoil (2026). https://docs.tinfoil.sh/verification/attestation-architecture
6. How verification works in Tinfoil, Tinfoil (2026). https://docs.tinfoil.sh/verification/verification-in-tinfoil
7. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). https://github.com/tinfoilsh/modelwrap
8. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). https://tee.fail/
9. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). https://arxiv.org/abs/2608.23375
10. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). https://batteringram.eu/
11. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). https://rmpocalypse.github.io/
12. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). https://www.amd.com/en/resources/product-security/bulletin/amd-sb-3020.html
13. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). https://techgov.intelligence.org/blog/on-tees-for-privacy-preserving-monitoring-in-ai-governance
14. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). https://arxiv.org/abs/2506.23706
15. Flexible Hardware-Enabled Guarantees for AI Compute, J. Petrie et al. (2025). https://arxiv.org/abs/2506.15093
16. Technical Options for Flexible Hardware-Enabled Guarantees, J. Petrie & O. Aarne (2025). https://arxiv.org/abs/2506.03409
17. International Security Applications of Flexible Hardware-Enabled Guarantees, O. Aarne & J. Petrie (2025). https://arxiv.org/abs/2506.15100
18. Hardware-Enabled Governance Mechanisms: Developing Technical Solutions to Exempt Items Otherwise Classified Under Export Control Classification Numbers 3A090 and 4A090, G. Kulp et al. (2024). https://www.rand.org/pubs/working_papers/WRA3056-1.html
19. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). https://www.cnas.org/publications/reports/secure-governable-chips
20. Hardware-Enabled Mechanisms for Verifying Responsible AI Development, A. O'Gara et al. (2025). https://arxiv.org/abs/2505.03742
21. Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors, N. Cankaya et al. (2026). https://arxiv.org/abs/2606.10724
22. The Fundamentals and Feasibility of Secure Network Taps for Verifying AI Datacenter Use, N. Cankaya (2026). https://nacicankaya.substack.com/p/research-note-the-fundamentals-and
23. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). https://intelligence.org/wp-content/uploads/2026/06/A-system-overview-for-near-term-low-trust-AI-compute-verification.pdf
24. Verification Plan, R. Dean (2026). https://ai-2040.com/supplements/verification-plan
25. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). https://amododesign.com/notes/2026-09-15-network-tap-inference-verification/
26. Amodo-Design/Inference-Recomputation-Prototype (GitHub repository), Amodo Design (2026). https://github.com/Amodo-Design/Inference-Recomputation-Prototype
27. inference-verification: Inference Verification Prototype, Singapore AI Safety Hub (SASH) (2026). https://github.com/sg-ai-safety-hub/inference-verification
28. Internationalising AI Verification, Singapore AI Safety Hub (SASH) (2026). https://www.aisafety.sg/research/internationalising-ai-verification
29. Network Tapping for AI Verification: A Technical Assessment, Amodo Design (2026). https://amododesign.com/notes/2026-05-03-network-tapping/
30. Network Traffic Hashing, Amodo Design (2026). https://amododesign.com/notes/2026-07-03-network-traffic-hashing/