# AI verification proposal

A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-09. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0015,M-0016&ready=R3

How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's development status, security evidence and findings. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and findings) and https://trustbutveri.fyi/about/readiness/ (development status).

## Filters

Filters apply to mechanisms only and describe the setting the proposal is for.

- **Minimum development status: Operational use.** Keeps mechanisms whose readiness level is at least this one. A level describes the public evidence for a mechanism's stated use, not its cost or feasibility. R3 can still have open critical flaws.

4 of 25 mechanisms on the map pass these filters.

## Overview

One row per mechanism, read from its record. Open failures: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees. Findings are grouped as known failures, scope limitations and open questions. Only known failures count as failures. Counts are an inventory of published findings, not a risk score.

| Mechanism | Development | Security evidence | Prover | Attack testing | Hardware | Open failures | Weights | Inputs and outputs | Training data |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Memory wiping and proofs of secure erasure (excluded by the filters) | Proposed | Published security analysis | Adversarial | Analysis | None | 0 / 1 / 0 | not involved | not involved | not involved |
| Timed challenge-response and memory-occupation challenges (excluded by the filters) | Research demonstration | Published security analysis | Adversarial | Analysis | None | 0 / 1 / 0 | not involved | not involved | not involved |

## Claims

No claims chosen.

## Mechanisms

### Memory wiping and proofs of secure erasure

Overwriting a device's memory in a way a verifier can check, so that data from earlier, undeclared work cannot persist in memory the wipe reaches. ([Memory wiping and proofs of secure erasure](https://trustbutveri.fyi/mechanisms/memory-wiping-and-secure-erasure/))

- Assessment: mechanism family.
- Development: Proposed (legacy code R1), assessed for showing that no data from earlier work persists in memory the wipe reaches.
- Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: none. Prover cooperation: required. Attack testing: analysis. Category: Isolation & system architectures.
- What the verifier sees: model weights not involved; inputs and outputs not involved; training data not involved. Overwrites memory with verifier-chosen data; it does not handle model data.
- Filter conflict: Development status: Proposed. Minimum: Operational use.

### Timed challenge-response and memory-occupation challenges

A verifier times answers to unpredictable questions designed so that answering correctly and in time requires holding specified data locally or dedicating specified resources. ([Timed challenge-response and memory-occupation challenges](https://trustbutveri.fyi/mechanisms/timed-challenge-response/))

- Assessment: mechanism family.
- Development: Research demonstration (legacy code R2), assessed for detecting whether a GPU is doing other work.
- Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: none. Prover cooperation: required. Attack testing: analysis. Category: Cryptographic & computational.
- What the verifier sees: model weights not involved; inputs and outputs not involved; training data not involved. Uses verifier-chosen challenges; it does not handle model data.
- Filter conflict: Development status: Research demonstration. Minimum: Operational use.


## Properties

Not counted as properties, because the filters exclude them: Memory wiping and proofs of secure erasure and Timed challenge-response and memory-occupation challenges.


## Attack testing

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

**Testing history**

- Memory wiping and proofs of secure erasure: Analysis (excluded by filters)
- Timed challenge-response and memory-occupation challenges: Analysis (excluded by filters)


## Limits

**Excluded by the filters**

- Memory wiping and proofs of secure erasure: Development status: Proposed. Minimum: Operational use.
- Timed challenge-response and memory-occupation challenges: Development status: Research demonstration. Minimum: Operational use.

**Open significant failures**

- Outside help during challenges (known failure, theoretical argument, in Memory wiping and proofs of secure erasure; https://trustbutveri.fyi/mechanisms/memory-wiping-and-secure-erasure/evidence/flaws/2/) [3][4]. Classic proofs of secure erasure assume the device is isolated during the protocol. Bursuc et al. relax this to a bound on how close a helper can be, enforced by round-trip times. In data centres, remote memory access has round trips of about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview therefore says verification depends on ruling out RDMA by latency or physical disconnection.

  Related mechanism: Timed challenge-response and memory-occupation challenges (R2, in the proposal). Timed challenges bound how far away a helper can be by how quickly it must answer.

  Related mechanism: Bandwidth limits and compartmentalization (R2, not in the proposal). Removing or capping links between groups of accelerators limits remote memory access during a challenge.
- Remote memory narrows the timing margin (known failure, theoretical argument, in Timed challenge-response and memory-occupation challenges; https://trustbutveri.fyi/mechanisms/timed-challenge-response/evidence/flaws/2/) [4]. Data-centre remote memory access returns in about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview says verification of memory saturation depends on ruling out remote access by latency or physical disconnection. It names pre-staging data into local memory as the remaining evasion and proposes an unpredictable, capacity-filling challenge to close it.

  Related mechanism: Bandwidth limits and compartmentalization (R2, not in the proposal). Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced.

**Scope limitations**

- Memory the wipe cannot reach (scope limitation, open question, in Memory wiping and proofs of secure erasure; https://trustbutveri.fyi/mechanisms/memory-wiping-and-secure-erasure/evidence/flaws/1/) [5][6]. Amodo's inventory of a GB200 system lists many memory stores beyond GPU HBM and host DRAM. It notes that SSD controller DRAM sits on a private bus that host commands cannot read or write, and that its optimized algorithm leaves 25 GiB of HBM unattested. It also asks how switch memory could be wiped.
- Gap between erased and total memory (scope limitation, theoretical argument, in Memory wiping and proofs of secure erasure; https://trustbutveri.fyi/mechanisms/memory-wiping-and-secure-erasure/evidence/flaws/3/) [3]. Bursuc et al. note that memory left between the erased region and the device's full memory could hold data, and that their bounds are tighter only against a restricted adversary.

**Open questions**

- Error rates not quantified (open question, open question, in Timed challenge-response and memory-occupation challenges; https://trustbutveri.fyi/mechanisms/timed-challenge-response/evidence/flaws/3/) [9]. Monfared et al. show separable timing distributions. Their acceptance rule passes a GPU when its mean time per round stays at or below a chosen maximum, and an appendix outlines statistical tests for the proof-of-work puzzle. They leave hardware-specific threshold values to future work and report no false-positive or false-negative rates.

**Not yet demonstrated**

- Memory wiping and proofs of secure erasure: Proposed (legacy code R1), assessed for showing that no data from earlier work persists in memory the wipe reaches


## Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open failure or a dependency. Pointers, not recommendations: each brings its own readiness level and findings, and none is claimed to close a failure.

- **Bandwidth limits and compartmentalization** (Research demonstration (legacy code R2), assessed for monitoring inter-node traffic with operator-run software on four GPUs). Excluded by the filters: development: Research demonstration
  - Bears on the open significant failure "Outside help during challenges" in Memory wiping and proofs of secure erasure. Removing or capping links between groups of accelerators limits remote memory access during a challenge.
  - Bears on the open significant failure "Remote memory narrows the timing margin" in Timed challenge-response and memory-occupation challenges. Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced.
  - Timed challenge-response and memory-occupation challenges waits on it: Outside help, such as remote memory, must be excluded during challenges.


## Dependencies

**Blockers**

- Memory wiping and proofs of secure erasure: Wipes take time: tens of minutes for a pod's volatile memory and hours for SSDs, displacing work. (performance & compatibility) [4][5][6]
- Memory wiping and proofs of secure erasure: Timed challenges must exclude remote memory and other helpers. (coverage & hidden compute; waits on Timed challenge-response and memory-occupation challenges) [3][4]
- Memory wiping and proofs of secure erasure: All memory stores in a system must be inventoried and wiped at the same time. (coverage & hidden compute) [5]
- Timed challenge-response and memory-occupation challenges: No network-level memory challenge across data-centre servers has been demonstrated. (adversarial validation) [4]
- Timed challenge-response and memory-occupation challenges: Challenges that fill memory displace workloads; filling a pod's volatile memory takes tens of minutes and SSDs take hours. (performance & compatibility) [4][9]
- Timed challenge-response and memory-occupation challenges: Outside help, such as remote memory, must be excluded during challenges. (coverage & hidden compute; waits on Bandwidth limits and compartmentalization) [4]


## What the verifier sees

- Model weights: shown by none; depends on the design for none; hidden by none; not involved in Memory wiping and proofs of secure erasure and Timed challenge-response and memory-occupation challenges; unspecified for none.
- Inputs and outputs: shown by none; depends on the design for none; hidden by none; not involved in Memory wiping and proofs of secure erasure and Timed challenge-response and memory-occupation challenges; unspecified for none.
- Training data: shown by none; depends on the design for none; hidden by none; not involved in Memory wiping and proofs of secure erasure and Timed challenge-response and memory-occupation challenges; unspecified for none.

## Implementations

- Memory wiping and proofs of secure erasure: [AI 2040 inference-only verification stack](https://trustbutveri.fyi/implementations/ai-2040-inference-only-verification-plan/) (R1, proposed architecture); [Low-trust AI compute verification system overview](https://trustbutveri.fyi/implementations/low-trust-compute-verification-system-overview/) (R1, proposed architecture)
- Timed challenge-response and memory-occupation challenges: [Data-centre memory challenging](https://trustbutveri.fyi/implementations/data-centre-memory-challenging/) (R1, proposed architecture); [GPU contention probes](https://trustbutveri.fyi/implementations/gpu-contention-probes/) (R2, research prototype); [Low-trust AI compute verification system overview](https://trustbutveri.fyi/implementations/low-trust-compute-verification-system-overview/) (R1, proposed architecture); [SAGE](https://trustbutveri.fyi/implementations/sage-gpu-attestation/) (R2, research prototype); [VRAM-residency challenge](https://trustbutveri.fyi/implementations/vram-residency-challenge/) (R2, research prototype)

## Sources

1. Verification Plan, R. Dean (2026). https://ai-2040.com/supplements/verification-plan
2. Secure Code Update for Embedded Devices via Proofs of Secure Erasure, D. Perito & G. Tsudik (2010). https://link.springer.com/chapter/10.1007/978-3-642-15497-3_39
3. Software-Based Memory Erasure with Relaxed Isolation Requirements, S. Bursuc et al. (2024). https://ieeexplore.ieee.org/document/10664348/
4. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). https://intelligence.org/wp-content/uploads/2026/06/A-system-overview-for-near-term-low-trust-AI-compute-verification.pdf
5. Memory Wipes - Performance Analysis, Amodo Design (2026). https://amododesign.com/notes/2026-07-01-memory-wiping/
6. Improving Disk Wiping Speed for Memory Wipes, Amodo Design (2026). https://amododesign.com/notes/2026-09-14-disk-wiping-speed/
7. Amodo-Design/PoSE-Memory-Wiping (GitHub repository), Amodo Design (2026). https://github.com/Amodo-Design/PoSE-Memory-Wiping
8. Empirical Evaluation of Memory-Erasure Protocols, R. Gil-Pons et al. (2025). https://www.scitepress.org/Papers/2025/135548/135548.pdf
9. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). https://arxiv.org/abs/2602.09369
10. SAGE: Software-based Attestation for GPU Execution, A. Ivanov et al. (2023). https://www.usenix.org/conference/atc23/presentation/ivanov
11. SWATT: SoftWare-based ATTestation for Embedded Devices, A. Seshadri et al. (2004). https://netsec.ethz.ch/publications/papers/swatt.pdf
12. Proofs of Space, S. Dziembowski et al. (2015). https://eprint.iacr.org/2013/796
13. On the Difficulty of Software-Based Attestation of Embedded Devices, C. Castelluccia et al. (2009). https://s3.eurecom.fr/docs/ccs09_Castelluccia.pdf
14. Refutation of "On the Difficulty of Software-Based Attestation of Embedded Devices", A. Perrig & L. van Doorn (2010). https://netsec.ethz.ch/publications/papers/perrig-ccs-refutation.pdf