# AI verification proposal

A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-09. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0016,M-0020,M-0012&tested=analysis

How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's development status, security evidence and findings. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and findings) and https://trustbutveri.fyi/about/readiness/ (development status).

## Filters

Filters apply to mechanisms only and describe the setting the proposal is for.

- **Attack testing: Published analysis.** Keeps mechanisms whose strongest published attack testing is at least this. The strongest published attempt to break the mechanism for its verification use: a security analysis, red-teaming by its developers or collaborators, or a red team independent of them.

24 of 25 mechanisms on the map pass these filters.

## Overview

One row per mechanism, read from its record. Open failures: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees. Findings are grouped as known failures, scope limitations and open questions. Only known failures count as failures. Counts are an inventory of published findings, not a risk score.

| Mechanism | Development | Security evidence | Prover | Attack testing | Hardware | Open failures | Weights | Inputs and outputs | Training data |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Timed challenge-response and memory-occupation challenges | Research demonstration | Published security analysis | Adversarial | Analysis | None | 0 / 1 / 0 | not involved | not involved | not involved |
| Remote detection of data centres | Proposed | Published security analysis | Adversarial | Analysis | None | 0 / 0 / 0 | not involved | not involved | not involved |
| Hardware-attested weight binding | Operational use | Published attack testing | Semi-trusted | Independent red-team | Existing features | 1 / 0 / 0 | hidden | unspecified | not involved |

## Claims

No claims chosen.

## Mechanisms

### Timed challenge-response and memory-occupation challenges

A verifier times answers to unpredictable questions designed so that answering correctly and in time requires holding specified data locally or dedicating specified resources. ([Timed challenge-response and memory-occupation challenges](https://trustbutveri.fyi/mechanisms/timed-challenge-response/))

- Assessment: mechanism family.
- Development: Research demonstration (legacy code R2), assessed for detecting whether a GPU is doing other work.
- Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: none. Prover cooperation: required. Attack testing: analysis. Category: Cryptographic & computational.
- What the verifier sees: model weights not involved; inputs and outputs not involved; training data not involved. Uses verifier-chosen challenges; it does not handle model data.

### Remote detection of data centres

Remote detection locates large data centres and estimates their power capacity without site access, using satellite imagery, heat signatures and public records such as permits. ([Remote detection of data centres](https://trustbutveri.fyi/mechanisms/remote-detection-of-data-centres/))

- Assessment: mechanism family.
- Development: Proposed (legacy code R1), assessed for finding undeclared data centres above an agreed compute threshold.
- Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: none. Prover cooperation: not required. Attack testing: analysis. Category: Remote & side-channel sensing.
- What the verifier sees: model weights not involved; inputs and outputs not involved; training data not involved. Works from outside the facility; it does not handle model data.

### Hardware-attested weight binding

Checks that a hardware enclave serves committed model weights, by attesting software that tests the weights against a hash commitment when they are read. ([Hardware-attested weight binding](https://trustbutveri.fyi/mechanisms/model-identity-attestation/))

- Assessment: mechanism family.
- Development: Operational use (legacy code R3), assessed for hardware-attested weight binding showing users that a service runs its committed weights.
- Security evidence: Published attack testing. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: semi-trusted prover. Hardware: existing features. Prover cooperation: required. Attack testing: independent red-team. Category: Cryptographic & computational.
- What the verifier sees: model weights hidden; inputs and outputs unspecified; training data not involved. Verifiers check a hash commitment to the weights, carried in a hardware attestation, and need no access to the weights themselves. The mechanism does not specify whether prompts and outputs are disclosed to a verifier. It involves no training data.


## Properties

**Operational use**

- Hardware-attested weight binding: Operational use (legacy code R3), assessed for hardware-attested weight binding showing users that a service runs its committed weights

**Built for an adversarial prover**

- Timed challenge-response and memory-occupation challenges
- Remote detection of data centres

**No new hardware needed**

- Timed challenge-response and memory-occupation challenges
- Remote detection of data centres
- Hardware-attested weight binding

**Failures since mitigated**

- Launch-state attestation does not by itself cover weights loaded later (in Hardware-attested weight binding) [16][26]


## Attack testing

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

**Testing history**

- Timed challenge-response and memory-occupation challenges: Analysis
- Remote detection of data centres: Analysis
- Hardware-attested weight binding: Independent red-team


## Limits

**Open critical failures**

- Underlying attestation can be forged or relayed (known failure, demonstrated attack, in Hardware-attested weight binding; https://trustbutveri.fyi/mechanisms/model-identity-attestation/evidence/flaws/1/) [17][18][22][23][24][25]. Inherited finding. Critical for weight binding against an operator with physical access to affected hardware, or with control of the hypervisor on an AMD SEV-SNP platform without AMD's fixes. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary. The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. Related finding: https://trustbutveri.fyi/mechanisms/tee-remote-attestation/evidence/flaws/1/.

  Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

  Related mechanism: Hardware-enabled guarantees (flexHEG) and guarantee processors (R1, not in the proposal). A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.

**Open significant failures**

- Remote memory narrows the timing margin (known failure, theoretical argument, in Timed challenge-response and memory-occupation challenges; https://trustbutveri.fyi/mechanisms/timed-challenge-response/evidence/flaws/2/) [1]. Data-centre remote memory access returns in about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview says verification of memory saturation depends on ruling out remote access by latency or physical disconnection. It names pre-staging data into local memory as the remaining evasion and proposes an unpredictable, capacity-filling challenge to close it.

  Related mechanism: Bandwidth limits and compartmentalization (R2, not in the proposal). Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced.

**Scope limitations**

- Facilities can be disguised or hidden (scope limitation, theoretical argument, in Remote detection of data centres; https://trustbutveri.fyi/mechanisms/remote-detection-of-data-centres/evidence/flaws/1/) [11]. Halstead and Larsen discuss two ways to hide a facility. One is to disguise it as a legitimate industrial site. The other is to build it underground, with cooling that avoids visible heat plumes. They note that the underground option requires bespoke engineering.
- Small sites may not be detectable (scope limitation, theoretical argument, in Remote detection of data centres; https://trustbutveri.fyi/mechanisms/remote-detection-of-data-centres/evidence/flaws/2/) [11][13]. Halstead and Larsen conclude that a sufficiently small covert project could not be ruled out with confidence. In their estimates, the chance of detection is lower for smaller sites. Krawec notes that small data centres in existing buildings may lack the distinctive features of large facilities.

  Related mechanism: Chip registries and manufacturing records (R1, not in the proposal). Accounts for chips from the fab onwards, which does not depend on a site being visible.
- For private models, a user can confirm consistency but not content (scope limitation, open question, in Hardware-attested weight binding; https://trustbutveri.fyi/mechanisms/model-identity-attestation/evidence/flaws/3/) [16][27]. When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy.

**Open questions**

- Error rates not quantified (open question, open question, in Timed challenge-response and memory-occupation challenges; https://trustbutveri.fyi/mechanisms/timed-challenge-response/evidence/flaws/3/) [3]. Monfared et al. show separable timing distributions. Their acceptance rule passes a GPU when its mean time per round stays at or below a chosen maximum, and an appendix outlines statistical tests for the proof-of-work puzzle. They leave hardware-specific threshold values to future work and report no false-positive or false-negative rates.
- Search for unknown sites is undemonstrated (open question, open question, in Remote detection of data centres; https://trustbutveri.fyi/mechanisms/remote-detection-of-data-centres/evidence/flaws/3/) [13]. Krawec reports that telling data centres apart from other industrial facilities systematically is difficult. Automating detection would need large amounts of training imagery and a purpose-trained model. In Krawec's words, automated data-centre detection "remains primarily conceptual at present".

**Not yet demonstrated**

- Remote detection of data centres: Proposed (legacy code R1), assessed for finding undeclared data centres above an agreed compute threshold


## Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open failure or a dependency. Pointers, not recommendations: each brings its own readiness level and findings, and none is claimed to close a failure.

- **Hardware-enabled guarantees (flexHEG) and guarantee processors** (Proposed (legacy code R1), assessed for checking and enforcing training-compute limits on chips, against adversaries up to states)
  - Bears on the open critical failure "Underlying attestation can be forged or relayed" in Hardware-attested weight binding. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
- **Bandwidth limits and compartmentalization** (Research demonstration (legacy code R2), assessed for monitoring inter-node traffic with operator-run software on four GPUs)
  - Bears on the open significant failure "Remote memory narrows the timing margin" in Timed challenge-response and memory-occupation challenges. Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced.
  - Timed challenge-response and memory-occupation challenges waits on it: Outside help, such as remote memory, must be excluded during challenges.
- **TEE remote attestation for AI workloads** (Operational use (legacy code R3), assessed for showing which software ran to a party that distrusts the operator holding the hardware)
  - Hardware-attested weight binding waits on it: Attestation that resists physical attackers, for the enclave variant.


## Dependencies

**Missing prerequisites**

- TEE remote attestation for AI workloads (Operational use (legacy code R3), assessed for showing which software ran to a party that distrusts the operator holding the hardware), needed by Hardware-attested weight binding

**Blockers**

- Timed challenge-response and memory-occupation challenges: No network-level memory challenge across data-centre servers has been demonstrated. (adversarial validation) [1]
- Timed challenge-response and memory-occupation challenges: Challenges that fill memory displace workloads; filling a pod's volatile memory takes tens of minutes and SSDs take hours. (performance & compatibility) [1][3]
- Timed challenge-response and memory-occupation challenges: Outside help, such as remote memory, must be excluded during challenges. (coverage & hidden compute; waits on Bandwidth limits and compartmentalization) [1]
- Remote detection of data centres: Wide-area, automated detection of data centres is not yet practical and needs large training datasets. (coverage & hidden compute) [13]
- Remote detection of data centres: No measured detection or false-alarm rates for finding undeclared facilities have been published. (adversarial validation) [11][13]
- Remote detection of data centres: Recent high-resolution imagery is costly, is limited by weather and needs trained analysts. (access & governance) [13]
- Hardware-attested weight binding: Attestation that resists physical attackers, for the enclave variant. (hardware trust; waits on TEE remote attestation for AI workloads) [22]


## What the verifier sees

- Model weights: shown by none; depends on the design for none; hidden by Hardware-attested weight binding; not involved in Timed challenge-response and memory-occupation challenges and Remote detection of data centres; unspecified for none.
- Inputs and outputs: shown by none; depends on the design for none; hidden by none; not involved in Timed challenge-response and memory-occupation challenges and Remote detection of data centres; unspecified for Hardware-attested weight binding.
- Training data: shown by none; depends on the design for none; hidden by none; not involved in Timed challenge-response and memory-occupation challenges, Remote detection of data centres and Hardware-attested weight binding; unspecified for none.

## Implementations

- Timed challenge-response and memory-occupation challenges: [Data-centre memory challenging](https://trustbutveri.fyi/implementations/data-centre-memory-challenging/) (R1, proposed architecture); [GPU contention probes](https://trustbutveri.fyi/implementations/gpu-contention-probes/) (R2, research prototype); [Low-trust AI compute verification system overview](https://trustbutveri.fyi/implementations/low-trust-compute-verification-system-overview/) (R1, proposed architecture); [SAGE](https://trustbutveri.fyi/implementations/sage-gpu-attestation/) (R2, research prototype); [VRAM-residency challenge](https://trustbutveri.fyi/implementations/vram-residency-challenge/) (R2, research prototype)
- Remote detection of data centres: none on the map
- Hardware-attested weight binding: [Attestable Audits](https://trustbutveri.fyi/implementations/attestable-audits/) (R2, research prototype); [PAL*M](https://trustbutveri.fyi/implementations/palm/) (R2, research prototype); [Tinfoil model identity (Modelwrap)](https://trustbutveri.fyi/implementations/tinfoil-model-identity/) (R3, product)

## Sources

1. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). https://intelligence.org/wp-content/uploads/2026/06/A-system-overview-for-near-term-low-trust-AI-compute-verification.pdf
2. Verification Plan, R. Dean (2026). https://ai-2040.com/supplements/verification-plan
3. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). https://arxiv.org/abs/2602.09369
4. SAGE: Software-based Attestation for GPU Execution, A. Ivanov et al. (2023). https://www.usenix.org/conference/atc23/presentation/ivanov
5. SWATT: SoftWare-based ATTestation for Embedded Devices, A. Seshadri et al. (2004). https://netsec.ethz.ch/publications/papers/swatt.pdf
6. Proofs of Space, S. Dziembowski et al. (2015). https://eprint.iacr.org/2013/796
7. Secure Code Update for Embedded Devices via Proofs of Secure Erasure, D. Perito & G. Tsudik (2010). https://link.springer.com/chapter/10.1007/978-3-642-15497-3_39
8. Software-Based Memory Erasure with Relaxed Isolation Requirements, S. Bursuc et al. (2024). https://ieeexplore.ieee.org/document/10664348/
9. On the Difficulty of Software-Based Attestation of Embedded Devices, C. Castelluccia et al. (2009). https://s3.eurecom.fr/docs/ccs09_Castelluccia.pdf
10. Refutation of "On the Difficulty of Software-Based Attestation of Embedded Devices", A. Perrig & L. van Doorn (2010). https://netsec.ethz.ch/publications/papers/perrig-ccs-refutation.pdf
11. Covert AI Projects, B. Halstead & T. Larsen (2026). https://ai-2040.com/supplements/covert-ai-projects
12. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). https://www.rand.org/pubs/working_papers/WRA4077-1.html
13. Tracking Hyperscale AI Data Center Growth with Satellite Imagery, C. Krawec (2026). https://fas.org/publication/tracking-hyperscale/
14. Introducing the Frontier Data Centers Hub, Epoch AI (2025). https://epoch.ai/latest/introducing-the-frontier-data-centers-hub
15. AI Data Centers Documentation – Methodology, Epoch AI (2026). https://epoch.ai/data/data-centers-documentation/methodology
16. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). https://tinfoil.sh/blog/2026-02-03-proving-model-identity
17. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). https://arxiv.org/abs/2601.16199
18. A primer on secure enclaves, Tinfoil (2026). https://docs.tinfoil.sh/verification/secure-enclave-primer
19. Backend infrastructure, Tinfoil (2026). https://docs.tinfoil.sh/verification/attestation-architecture
20. How verification works in Tinfoil, Tinfoil (2026). https://docs.tinfoil.sh/verification/verification-in-tinfoil
21. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). https://github.com/tinfoilsh/modelwrap
22. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). https://tee.fail/
23. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). https://batteringram.eu/
24. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). https://rmpocalypse.github.io/
25. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). https://www.amd.com/en/resources/product-security/bulletin/amd-sb-3020.html
26. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). https://techgov.intelligence.org/blog/on-tees-for-privacy-preserving-monitoring-in-ai-governance
27. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). https://arxiv.org/abs/2506.23706