# AI verification proposal

A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-09. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0018,M-0001&prover=adversarial

How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's development status, security evidence and findings. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and findings) and https://trustbutveri.fyi/about/readiness/ (development status).

## Filters

Filters apply to mechanisms only and describe the setting the proposal is for.

- **Prover: Adversarial.** Keeps mechanisms whose threat model holds against at least this prover. Adversarial is the strongest assumption. The prover is the party being checked. Semi-trusted designs rely on part of its stack: usually the chip vendor's hardware root of trust, its firmware or counters, or its supply-chain records. Adversarial designs aim to hold even if it cheats wherever the checks allow, within their stated assumptions.

19 of 25 mechanisms on the map pass these filters.

## Overview

One row per mechanism, read from its record. Open failures: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees. Findings are grouped as known failures, scope limitations and open questions. Only known failures count as failures. Counts are an inventory of published findings, not a risk score.

| Mechanism | Development | Security evidence | Prover | Attack testing | Hardware | Open failures | Weights | Inputs and outputs | Training data |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Chip location verification | Proposed | Published security analysis | Adversarial | Analysis | Existing features | 0 / 4 / 0 | not involved | not involved | not involved |
| Sampled inference recomputation | Operational use | Published security analysis | Adversarial | Analysis | None | 0 / 2 / 1 | depends | depends | not involved |

## Claims

No claims chosen.

## Mechanisms

### Chip location verification

Timing a chip's signed replies to trusted servers at known places, so that the speed of light bounds how far away the chip can be. ([Chip location verification](https://trustbutveri.fyi/mechanisms/chip-location-verification/))

- Assessment: mechanism family.
- Development: Proposed (legacy code R1), assessed for bounding how far a chip is from trusted landmark servers when checked.
- Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: existing features. Prover cooperation: required. Attack testing: analysis. Category: Compute accounting & provenance.
- What the verifier sees: model weights not involved; inputs and outputs not involved; training data not involved. Times signed replies from chips; it does not handle model data.

### Sampled inference recomputation

A verifier re-runs a random sample of an AI provider's logged queries on a trusted copy of the declared model and checks the outputs match. ([Sampled inference recomputation](https://trustbutveri.fyi/mechanisms/sampled-inference-recomputation/))

- Assessment: mechanism family.
- Development: Operational use (legacy code R3), assessed for checking untrusted workers' activations against the declared model, prompt and precision.
- Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: none. Prover cooperation: required. Attack testing: analysis. Category: Cryptographic & computational.
- What the verifier sees: model weights depends; inputs and outputs depends; training data not involved. Recomputation needs the weights and sampled requests inside the checking environment. For closed models, the record describes a trusted, confidential environment; disclosure to the verifier depends on that boundary.


## Properties

**Operational use**

- Sampled inference recomputation: Operational use (legacy code R3), assessed for checking untrusted workers' activations against the declared model, prompt and precision

**Built for an adversarial prover**

- Chip location verification
- Sampled inference recomputation

**No new hardware needed**

- Chip location verification
- Sampled inference recomputation


## Attack testing

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

**Testing history**

- Chip location verification: Analysis
- Sampled inference recomputation: Analysis


## Limits

**Open significant failures**

- Extracting a chip's key lets another device answer for it (known failure, theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/evidence/flaws/1/) [1][6]. Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM.
- Added delay can shift an estimated position (known failure, demonstrated attack, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/evidence/flaws/2/) [1][4]. Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location.
- Faster-than-assumed network paths (known failure, theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/evidence/flaws/3/) [1][4]. Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often.
- Compromised landmarks can falsify measurements (known failure, theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/evidence/flaws/4/) [1][4][5]. A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators.
- Tolerance for numerical noise leaves a covert channel (known failure, demonstrated attack, in Sampled inference recomputation; https://trustbutveri.fyi/mechanisms/sampled-inference-recomputation/evidence/flaws/1/) [8][16][19]. Schemes that accept approximate matches can put an upper bound on an adversary's covert bandwidth, but they cannot close the channel. The weight-exfiltration detector cut exfiltratable information to under 0.5%, not to zero, on a 30-billion-parameter mixture-of-experts model under benign prompt traffic. Its authors called the channel's size under adversarial prompts an open empirical question. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token. Across six models, that cut the slowdown from 146–254 times under benign prompts to 60–118 times. The attack widens the exfiltration bound. It does not target the check that outputs match the declared model.

  Related mechanism: Deterministic and bit-exact inference (R3, not in the proposal). Bit-exact inference would remove the numerical tolerance if exact replay can be deployed with the required weights and configuration.
- Some inference optimizations are not covered (known failure, theoretical argument, in Sampled inference recomputation; https://trustbutveri.fyi/mechanisms/sampled-inference-recomputation/evidence/flaws/3/) [9][10]. TOPLOC's authors state that it cannot detect speculative decoding in which a cheaper model does the decoding. They did not test whether it distinguishes types of key-value (KV) cache compression. DiFR was evaluated only on sampling from a single model. Its authors sketch an extension to one speculative-decoding algorithm but do not test it.

**Open minor failures**

- Mixed hardware widens the honest baseline (known failure, open question, in Sampled inference recomputation; https://trustbutveri.fyi/mechanisms/sampled-inference-recomputation/evidence/flaws/4/) [9]. When honest reference runs span different GPU types, the spread of benign scores grows. In DiFR's tests on Qwen3-30B-A3B, pooling A100 and H200 runs left Token-DiFR unable to separate the two smallest tested changes, a temperature of 1.1 instead of 1.0 and a simulated top-2 sampling bug, at the target false-positive rate, while cross-entropy separated them. Matched provider and verifier environments, or pooling that weights rare large deviations, restored detection.

**Scope limitations**

- Only recorded traffic is checked (scope limitation, theoretical argument, in Sampled inference recomputation; https://trustbutveri.fyi/mechanisms/sampled-inference-recomputation/evidence/flaws/2/) [8][20]. Recomputation checks that recorded, declared workloads are correct. It cannot show that the record is complete. The published schemes do not cover hidden workloads run on the same compute, or substituted work. Rinberg et al. say their exfiltration-detection scheme cannot stand alone.

  Related mechanism: Network taps and certifiers (R1, not in the proposal). Taps copy and hash all traffic on the monitored links, which bears on whether the traffic record is complete. They do not show what else ran on the same chips.

**Not yet demonstrated**

- Chip location verification: Proposed (legacy code R1), assessed for bounding how far a chip is from trusted landmark servers when checked


## Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open failure or a dependency. Pointers, not recommendations: each brings its own readiness level and findings, and none is claimed to close a failure.

- **Deterministic and bit-exact inference** (Operational use (legacy code R3), assessed for reproducing open-model inference from receipts in Gensyn's information-market service)
  - Bears on the open significant failure "Tolerance for numerical noise leaves a covert channel" in Sampled inference recomputation. Bit-exact inference would remove the numerical tolerance if exact replay can be deployed with the required weights and configuration.
- **Network taps and certifiers** (Proposed (legacy code R1), assessed for committing a complete record of cluster traffic, so declared inference can be checked)
  - Sampled inference recomputation waits on it: In tap-based retrofit designs, recording all inference traffic needs network taps and recomputation servers that can ingest it, in the worst case one recomputation-server network interface per inference front-end interface.
- **TEE remote attestation for AI workloads** (Operational use (legacy code R3), assessed for showing which software ran to a party that distrusts the operator holding the hardware). Excluded by the filters: assumes a semi-trusted prover
  - Chip location verification depends on it.


## Dependencies

**Missing prerequisites**

- TEE remote attestation for AI workloads (Operational use (legacy code R3), assessed for showing which software ran to a party that distrusts the operator holding the hardware), needed by Chip location verification

**Blockers**

- Chip location verification: No public code or reproducible end-to-end location results are available for the reported H100 prototype. (adversarial validation) [2][3]
- Chip location verification: Per-chip keys must be provisioned and protected against extraction; hardware-integrated, tamper-resistant versions still need R&D. (hardware trust) [1][6][22]
- Chip location verification: The time limit forces a trade-off: a limit at the speed of light in fibre can be beaten by faster links, while one at the vacuum speed of light makes honest chips fail often. (protocol soundness) [1]
- Chip location verification: A trusted landmark network must be built and secured, and who should operate it, under what oversight, is unsettled. (access & governance) [1][4]
- Sampled inference recomputation: In tap-based retrofit designs, recording all inference traffic needs network taps and recomputation servers that can ingest it, in the worst case one recomputation-server network interface per inference front-end interface. (coverage & hidden compute; waits on Network taps and certifiers) [15][23]
- Sampled inference recomputation: In retrofit designs, the recomputation server must sit inside the prover's data centre, possibly under the prover's physical control, and still be protected from a compromised provider, which Amodo rates 'not on track'. (hardware trust) [8][15]
- Sampled inference recomputation: No independent red-team of a recomputation consistency check has been published (the one independent attack study targets the weight-exfiltration bound), and Amodo rates recomputation red-teaming 'not started'. (adversarial validation) [15][16]
- Sampled inference recomputation: Tolerance-based checks need calibration on trusted hardware and exact knowledge of the provider's sampling procedure, and in one prototype a sampling-implementation mismatch produced large spurious differences. (performance & compatibility) [9][14]
- Sampled inference recomputation: The verifier needs the model weights, so checking a closed-weights model requires a trusted, confidential recomputation environment, which the retrofit designs place inside the prover's facility. (privacy & leakage) [9][20][21]


## What the verifier sees

- Model weights: shown by none; depends on the design for Sampled inference recomputation; hidden by none; not involved in Chip location verification; unspecified for none.
- Inputs and outputs: shown by none; depends on the design for Sampled inference recomputation; hidden by none; not involved in Chip location verification; unspecified for none.
- Training data: shown by none; depends on the design for none; hidden by none; not involved in Chip location verification and Sampled inference recomputation; unspecified for none.

## Implementations

- Chip location verification: [Lucid sovereignty (location) certificates](https://trustbutveri.fyi/implementations/lucid-location-certificates/) (R1, standard)
- Sampled inference recomputation: [AI 2040 inference-only verification stack](https://trustbutveri.fyi/implementations/ai-2040-inference-only-verification-plan/) (R1, proposed architecture); [DiFR (Divergence From Reference)](https://trustbutveri.fyi/implementations/difr/) (R2, research prototype); [Low-trust AI compute verification system overview](https://trustbutveri.fyi/implementations/low-trust-compute-verification-system-overview/) (R1, proposed architecture); [SASH confidential network logger](https://trustbutveri.fyi/implementations/sash-confidential-network-logger/) (R1, research prototype); [TOPLOC](https://trustbutveri.fyi/implementations/toploc/) (R3, open-source project)

## Sources

1. Location Verification for AI Chips, A. Brass & O. Aarne (2024). https://www.iaps.ai/research/location-verification-for-ai-chips
2. Location Verification for AI Chips (issue brief), A. Brass (2025). https://static1.squarespace.com/static/64edf8e7f2b10d716b5ba0e1/t/6827b67275666f3757f134ea/1747433075281/Location+Verification+two-pager.pdf
3. Ping-based Location, Ulyssean (2025). https://ping-location.info/
4. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). https://www.iaps.ai/research/near-term-verification-methods-for-ai-chip-exports
5. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). https://github.com/Lucid-Computing/sovereignty-certificate-specification
6. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). https://arxiv.org/abs/2605.01930
7. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). https://www.cnas.org/publications/reports/secure-governable-chips
8. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). https://arxiv.org/abs/2511.02620
9. DiFR: Inference Verification Despite Nondeterminism, A. Karvonen et al. (2025). https://arxiv.org/abs/2511.20621
10. TOPLOC: A Locality Sensitive Hashing Scheme for Trustless Verifiable Inference, J. M. Ong et al. (2025). https://proceedings.mlr.press/v267/ong25a.html
11. PrimeIntellect-ai/toploc (GitHub repository), Prime Intellect (2025). https://github.com/PrimeIntellect-ai/toploc
12. INTELLECT-2: A Reasoning Model Trained Through Globally Decentralized Reinforcement Learning, Prime Intellect Team et al. (2025). https://arxiv.org/abs/2505.07291
13. adamkarvonen/difr (GitHub repository), A. Karvonen (2025). https://github.com/adamkarvonen/difr
14. Scaling Recomputation Inference Verification, Amodo Design (2026). https://amododesign.com/notes/2026-09-02-scaling-recomputation-inference-verification/
15. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). https://amododesign.com/ai-verification/plan-a-sitrep/
16. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). https://arxiv.org/abs/2608.23375
17. SYNTHETIC-2 Release: Four Million Collaboratively Generated Reasoning Traces, Prime Intellect (2025). https://www.primeintellect.ai/blog/synthetic-2-release
18. An Inference Verification Prototype — Stage 1, Amodo Design (2026). https://amododesign.com/notes/2026-06-29-inference-verification-prototype/
19. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). https://arxiv.org/abs/2606.00279
20. Example Schemes for Verifying High-Stakes AI Agreements, Amodo Design (2026). https://amododesign.com/notes/2026-06-23-verification-algorithms/
21. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). https://intelligence.org/wp-content/uploads/2026/06/A-system-overview-for-near-term-low-trust-AI-compute-verification.pdf
22. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). https://arxiv.org/abs/2604.04712
23. Verification Plan, R. Dean (2026). https://ai-2040.com/supplements/verification-plan