# AI verification proposal

A proposal built with the Proposal Explorer of the AI Verification Tech Map (https://trustbutveri.fyi/), from its records of 2026-10-09. Interactive version: https://trustbutveri.fyi/explorer/?mechanisms=M-0018,M-0002,M-0024&tested=analysis

How to read it: a claim is something one party wants to verify about another's AI hardware or software. A mechanism is a general technique for verifying claims; it is "aimed at" a claim when that is its direct purpose, and "supporting" when it contributes without being aimed at it. A claim is addressed when a mechanism in the proposal is aimed at it and is not excluded by the filters; addressed does not mean verified, so check that mechanism's development status, security evidence and findings. Definitions: https://trustbutveri.fyi/about/methodology/ (roles, properties and findings) and https://trustbutveri.fyi/about/readiness/ (development status).

## Filters

Filters apply to mechanisms only and describe the setting the proposal is for.

- **Attack testing: Published analysis.** Keeps mechanisms whose strongest published attack testing is at least this. The strongest published attempt to break the mechanism for its verification use: a security analysis, red-teaming by its developers or collaborators, or a red team independent of them.

24 of 25 mechanisms on the map pass these filters.

## Overview

One row per mechanism, read from its record. Open failures: critical / significant / minor. The last three columns are the editors' reading of what the verifier sees. Findings are grouped as known failures, scope limitations and open questions. Only known failures count as failures. Counts are an inventory of published findings, not a risk score.

| Mechanism | Development | Security evidence | Prover | Attack testing | Hardware | Open failures | Weights | Inputs and outputs | Training data |
| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
| Chip location verification | Proposed | Published security analysis | Adversarial | Analysis | Existing features | 0 / 4 / 0 | not involved | not involved | not involved |
| Deterministic and bit-exact inference | Operational use | Published security analysis | Adversarial | Analysis | None | 0 / 0 / 0 | depends | depends | not involved |
| Bounding unexplained information in outputs | Research demonstration | Published attack testing | Adversarial | Independent red-team | Retrofit device | 0 / 1 / 0 | depends | depends | not involved |

## Claims

No claims chosen.

## Mechanisms

### Chip location verification

Timing a chip's signed replies to trusted servers at known places, so that the speed of light bounds how far away the chip can be. ([Chip location verification](https://trustbutveri.fyi/mechanisms/chip-location-verification/))

- Assessment: mechanism family.
- Development: Proposed (legacy code R1), assessed for bounding how far a chip is from trusted landmark servers when checked.
- Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: existing features. Prover cooperation: required. Attack testing: analysis. Category: Compute accounting & provenance.
- What the verifier sees: model weights not involved; inputs and outputs not involved; training data not involved. Times signed replies from chips; it does not handle model data.

### Deterministic and bit-exact inference

Making model inference reproducible bit for bit, so that a verifier's re-run must match the provider's output exactly rather than approximately. ([Deterministic and bit-exact inference](https://trustbutveri.fyi/mechanisms/deterministic-inference/))

- Assessment: mechanism family.
- Development: Operational use (legacy code R3), assessed for reproducing open-model inference from receipts in Gensyn's information-market service.
- Security evidence: Published security analysis. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: none. Prover cooperation: required. Attack testing: analysis. Category: Cryptographic & computational.
- What the verifier sees: model weights depends; inputs and outputs depends; training data not involved. Exact replay needs the weights, configuration and replayed requests inside the recomputation environment. What the verifier sees depends on whether that environment keeps them confidential.

### Bounding unexplained information in outputs

Limits the hidden information a facility's outputs can carry by measuring how much of those outputs the declared computation fails to predict. ([Bounding unexplained information in outputs](https://trustbutveri.fyi/mechanisms/bounding-unexplained-information/))

- Assessment: mechanism family.
- Development: Research demonstration (legacy code R2), assessed for bounding how much hidden information can leave in checked inference outputs.
- Security evidence: Published attack testing. Independent evaluation: unassessed. Formal proof: unassessed. Deployment assurance: unassessed.
- Claims in this proposal: none of them.
- Threat model: adversarial prover. Hardware: retrofit device. Prover cooperation: required. Attack testing: independent red-team. Category: Isolation & system architectures.
- What the verifier sees: model weights depends; inputs and outputs depends; training data not involved. Depends on where recomputation runs: in a sealed enclosure, or with zero-knowledge proofs, the verifier need not see the weights or the traffic.


## Properties

**Operational use**

- Deterministic and bit-exact inference: Operational use (legacy code R3), assessed for reproducing open-model inference from receipts in Gensyn's information-market service

**Built for an adversarial prover**

- Chip location verification
- Deterministic and bit-exact inference
- Bounding unexplained information in outputs

**No new hardware needed**

- Chip location verification
- Deterministic and bit-exact inference


## Attack testing

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

**Testing history**

- Chip location verification: Analysis
- Deterministic and bit-exact inference: Analysis
- Bounding unexplained information in outputs: Independent red-team


## Limits

**Open significant failures**

- Extracting a chip's key lets another device answer for it (known failure, theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/evidence/flaws/1/) [1][6]. Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM.
- Added delay can shift an estimated position (known failure, demonstrated attack, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/evidence/flaws/2/) [1][4]. Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location.
- Faster-than-assumed network paths (known failure, theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/evidence/flaws/3/) [1][4]. Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often.
- Compromised landmarks can falsify measurements (known failure, theoretical argument, in Chip location verification; https://trustbutveri.fyi/mechanisms/chip-location-verification/evidence/flaws/4/) [1][4][5]. A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators.
- Prompt-controlled entropy inflation widens the covert channel (known failure, demonstrated attack, in Bounding unexplained information in outputs; https://trustbutveri.fyi/mechanisms/bounding-unexplained-information/evidence/flaws/1/) [20][21]. Gumbel-based inference verification tolerates token choices that honest GPU nondeterminism could produce, and the size of that tolerated set grows with the model's output entropy. Kezins, an independent researcher, showed that an adversary who controls the prompt distribution can raise output entropy and roughly double the bits leaked per token. Across six models of 1 to 32 billion parameters, this cut the slowdown from 146–254 times under benign prompts to 60–118 times. Kezins argues that architectures built on the same unexplained-information bound inherit this attack surface, and recommends calibrating tolerances against local token entropy rather than benign traffic.

  Related mechanism: Deterministic and bit-exact inference (R3, in the proposal). Bit-exact replay would remove the tolerance for numerical noise that sets the size of this channel. The record notes that it needs full hardware and software metadata.

**Scope limitations**

- Some kernels remain genuinely nondeterministic (scope limitation, open question, in Deterministic and bit-exact inference; https://trustbutveri.fyi/mechanisms/deterministic-inference/evidence/flaws/1/) [8]. The bit-exact work separates kernels that are deterministic but not batch-invariant from truly nondeterministic ones that use atomic functions. Some integer de-quantization kernels use atomic additions and remain nondeterministic, so exact replay needs backends that avoid them.
- Cross-hardware replay relies on reverse-engineered, closed behaviour (scope limitation, open question, in Deterministic and bit-exact inference; https://trustbutveri.fyi/mechanisms/deterministic-inference/evidence/flaws/2/) [8][10]. Emulating one GPU's rounding on another requires reverse-engineering tensor-core arithmetic and modelling proprietary kernel choices. Hawkeye covers a subset of NVIDIA architectures and states that attention and other higher-level operations need further reverse engineering. For the bit-exact emulator, a proprietary Hopper kernel family is an open edge case.
- Information the declared computation explains is not bounded (scope limitation, theoretical argument, in Bounding unexplained information in outputs; https://trustbutveri.fyi/mechanisms/bounding-unexplained-information/evidence/flaws/2/) [19][22]. The bound limits unexplained bits only. Outputs that the declared computation fully explains can still carry valuable information: a compression study notes that an adversary with inference access can extract more proprietary information per bit than naive transmission allows.
- Channels other than checked outputs are outside the bound (scope limitation, theoretical argument, in Bounding unexplained information in outputs; https://trustbutveri.fyi/mechanisms/bounding-unexplained-information/evidence/flaws/3/) [18][20]. The inference-verification scheme treats side channels as out of scope. A low-trust system design argues that suppressing physical covert bandwidth below kilobits per second is much more achievable than aiming for zero, and that a malicious device can leak one bit of information by deliberately outputting a wrong result.

  Related mechanism: Side-channel suppression for isolated facilities (R1, not in the proposal). Physical side channels need separate suppression, which is this mechanism's purpose.

**Open questions**

- The facility-level design is untested (open question, open question, in Bounding unexplained information in outputs; https://trustbutveri.fyi/mechanisms/bounding-unexplained-information/evidence/flaws/4/) [19]. The compute-verification architecture is described with protocol details, potential attacks and prototyping plans, but no prototype results have been published.

**Not yet demonstrated**

- Chip location verification: Proposed (legacy code R1), assessed for bounding how far a chip is from trusted landmark servers when checked


## Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open failure or a dependency. Pointers, not recommendations: each brings its own readiness level and findings, and none is claimed to close a failure.

- **Bandwidth limits and compartmentalization** (Research demonstration (legacy code R2), assessed for monitoring inter-node traffic with operator-run software on four GPUs)
  - Bounding unexplained information in outputs waits on it: The prover's compute must be isolated so that all traffic passes through the verifier's interlock; any unmonitored path voids the bound.
- **Side-channel suppression for isolated facilities** (Proposed (legacy code R1), assessed for bounding physical covert channels out of a verified enclosure)
  - Bounding unexplained information in outputs waits on it: Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target.
- **Sampled inference recomputation** (Operational use (legacy code R3), assessed for checking untrusted workers' activations against the declared model, prompt and precision)
  - Bounding unexplained information in outputs depends on it.
- **TEE remote attestation for AI workloads** (Operational use (legacy code R3), assessed for showing which software ran to a party that distrusts the operator holding the hardware)
  - Chip location verification depends on it.
- **Network taps and certifiers** (Proposed (legacy code R1), assessed for committing a complete record of cluster traffic, so declared inference can be checked)
  - Bounding unexplained information in outputs depends on it.


## Dependencies

**Missing prerequisites**

- TEE remote attestation for AI workloads (Operational use (legacy code R3), assessed for showing which software ran to a party that distrusts the operator holding the hardware), needed by Chip location verification
- Sampled inference recomputation (Operational use (legacy code R3), assessed for checking untrusted workers' activations against the declared model, prompt and precision), needed by Bounding unexplained information in outputs
- Bandwidth limits and compartmentalization (Research demonstration (legacy code R2), assessed for monitoring inter-node traffic with operator-run software on four GPUs), needed by Bounding unexplained information in outputs
- Side-channel suppression for isolated facilities (Proposed (legacy code R1), assessed for bounding physical covert channels out of a verified enclosure), needed by Bounding unexplained information in outputs
- Network taps and certifiers (Proposed (legacy code R1), assessed for committing a complete record of cluster traffic, so declared inference can be checked), needed by Bounding unexplained information in outputs

**Blockers**

- Chip location verification: No public code or reproducible end-to-end location results are available for the reported H100 prototype. (adversarial validation) [2][3]
- Chip location verification: Per-chip keys must be provisioned and protected against extraction; hardware-integrated, tamper-resistant versions still need R&D. (hardware trust) [1][6][23]
- Chip location verification: The time limit forces a trade-off: a limit at the speed of light in fibre can be beaten by faster links, while one at the vacuum speed of light makes honest chips fail often. (protocol soundness) [1]
- Chip location verification: A trusted landmark network must be built and secured, and who should operate it, under what oversight, is unsettled. (access & governance) [1][4]
- Deterministic and bit-exact inference: Batch-invariant kernels cost throughput: in Thinking Machines' Qwen3-8B test, an improved deterministic build took 42 s against 26 s for vLLM's default, and SGLang reports an average 34.35% slowdown on its FlashInfer and FlashAttention 3 backends. (performance & compatibility) [9][11]
- Deterministic and bit-exact inference: Coverage is incomplete: the bit-exact emulator targets dense blocks on NVIDIA GPUs and excludes mixture-of-experts inference and training, and vLLM's batch-invariant mode is in beta, with open work on AMD hardware and speculative decoding. (performance & compatibility) [8][12][24]
- Deterministic and bit-exact inference: Amodo's status page for the AI 2040 verification plan rates a reproducible inference stack for that plan as 'not started'. (performance & compatibility) [25]
- Deterministic and bit-exact inference: Exact replay requires the prover to disclose weights, software versions, parallelism and batch sizes to whoever recomputes. (privacy & leakage) [8][18]
- Bounding unexplained information in outputs: The prover's compute must be isolated so that all traffic passes through the verifier's interlock; any unmonitored path voids the bound. (coverage & hidden compute; waits on Bandwidth limits and compartmentalization) [19]
- Bounding unexplained information in outputs: Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target. (coverage & hidden compute; waits on Side-channel suppression for isolated facilities) [18][20]
- Bounding unexplained information in outputs: Tolerance for numerical nondeterminism sets the size of the residual channel; bit-exact replay would remove it but needs full hardware and software metadata. (protocol soundness; waits on Deterministic and bit-exact inference) [18][21]
- Bounding unexplained information in outputs: Recomputation over confidential weights and inputs needs a protected setting: prover recomputation in a verifier-controlled enclosure, verifier recomputation in a prover-controlled enclosure, or zero-knowledge proofs. (privacy & leakage) [19]
- Bounding unexplained information in outputs: No prototype of the facility-level architecture exists to red-team. (adversarial validation) [19]


## What the verifier sees

- Model weights: shown by none; depends on the design for Deterministic and bit-exact inference and Bounding unexplained information in outputs; hidden by none; not involved in Chip location verification; unspecified for none.
- Inputs and outputs: shown by none; depends on the design for Deterministic and bit-exact inference and Bounding unexplained information in outputs; hidden by none; not involved in Chip location verification; unspecified for none.
- Training data: shown by none; depends on the design for none; hidden by none; not involved in Chip location verification, Deterministic and bit-exact inference and Bounding unexplained information in outputs; unspecified for none.

## Implementations

- Chip location verification: [Lucid sovereignty (location) certificates](https://trustbutveri.fyi/implementations/lucid-location-certificates/) (R1, standard)
- Deterministic and bit-exact inference: [Batch-invariant inference kernels (Thinking Machines)](https://trustbutveri.fyi/implementations/batch-invariant-inference-kernels/) (R2, open-source project); [Verde and RepOps (Gensyn)](https://trustbutveri.fyi/implementations/gensyn-verde-repops/) (R3, product); [Low-trust AI compute verification system overview](https://trustbutveri.fyi/implementations/low-trust-compute-verification-system-overview/) (R1, proposed architecture)
- Bounding unexplained information in outputs: none on the map

## Sources

1. Location Verification for AI Chips, A. Brass & O. Aarne (2024). https://www.iaps.ai/research/location-verification-for-ai-chips
2. Location Verification for AI Chips (issue brief), A. Brass (2025). https://static1.squarespace.com/static/64edf8e7f2b10d716b5ba0e1/t/6827b67275666f3757f134ea/1747433075281/Location+Verification+two-pager.pdf
3. Ping-based Location, Ulyssean (2025). https://ping-location.info/
4. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). https://www.iaps.ai/research/near-term-verification-methods-for-ai-chip-exports
5. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). https://github.com/Lucid-Computing/sovereignty-certificate-specification
6. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). https://arxiv.org/abs/2605.01930
7. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). https://www.cnas.org/publications/reports/secure-governable-chips
8. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). https://arxiv.org/abs/2606.00279
9. Defeating Nondeterminism in LLM Inference, H. He & Thinking Machines Lab (2025). https://thinkingmachines.ai/blog/defeating-nondeterminism-in-llm-inference/
10. Hawkeye: Reproducing GPU-Level Non-Determinism, E. Badash et al. (2026). https://proceedings.mlsys.org/paper_files/paper/2026/hash/e217c271a57c365a246b0ad39e668ba8-Abstract-Conference.html
11. Towards Deterministic Inference in SGLang and Reproducible RL Training, The SGLang Team (2025). https://www.lmsys.org/blog/2025-09-22-sglang-deterministic/
12. Batch Invariance (vLLM documentation), vLLM project (2026). https://github.com/vllm-project/vllm/blob/main/docs/features/batch_invariance.md
13. gensyn-ai/ree: Gensyn Reproducible Execution Environment (GitHub repository), Gensyn (2026). https://github.com/gensyn-ai/ree
14. EigenCloud Brings Verifiable AI to Mass Market with EigenAI and EigenCompute Launches, EigenCloud (2025). https://www.eigenlabs.org/blog/eigencloud-brings-verifiable-ai-to-mass-market-with-eigenai-and-eigencompute-launches/
15. Building Delphi: Pricing, Settlement, and Agentic Trading, D. Jedamski (2026). https://www.gensyn.ai/blog/building-delphi-pricing-settlement-and-agentic-trading
16. Reproducible Execution Environment (REE) (Gensyn documentation), Gensyn (2026). https://docs.gensyn.ai/tech
17. What is Delphi? (Delphi documentation), Gensyn (2026). https://docs.delphi.fyi/
18. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). https://intelligence.org/wp-content/uploads/2026/06/A-system-overview-for-near-term-low-trust-AI-compute-verification.pdf
19. Verifying AI Compute by Bounding Unexplained Information Exfiltration, J. Petrie & Y. Mühlhäuser (2026). https://openreview.net/forum?id=qtgG5HZSsk
20. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). https://arxiv.org/abs/2511.02620
21. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). https://arxiv.org/abs/2608.23375
22. Haiku to Opus in Just 10 bits: LLMs Unlock Large Compression Gains, R. Rinberg et al. (2026). https://arxiv.org/abs/2604.02343
23. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). https://arxiv.org/abs/2604.04712
24. [Feature]: Batch Invariant Feature and Performance Optimization (vLLM issue #27433), vLLM project contributors (2025). https://github.com/vllm-project/vllm/issues/27433
25. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). https://amododesign.com/ai-verification/plan-a-sitrep/