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A verification proposal from the AI Verification Tech Map, from its records of 2026-10-08. https://trustbutveri.fyi/explorer/?mechanisms=M-0022,M-0001,M-0016&implementations=M-0022:I-0010

Claims

Mechanisms3

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Analysis

Applied filters: none. Every filter is set to Any.

  • Open flaws: n critical n significant n minor
Claim coverageNo claims yet

Add claims to see which ones the mechanisms address.

Properties1 in production · 2 built for an adversarial prover
In production
Attack testing3 mechanisms with published testing

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

Limits1 family with findings to check · 1 not yet demonstrated · 3 mechanisms with open significant findings
Family findings
  • Side-channel suppression for isolated facilities

    Context for RAND secure inference data center (SIDC) design. These findings concern the family or other implementations; applicability must be checked against their stated scope.

    • Supply-chain implants may evade inspection in Side-channel suppression for isolated facilities

      Cankaya identifies malicious hardware embedded deep in purchased components as a residual risk that visual inspection and disassembly may not catch. He notes that radiographic examination under high-security standards could mitigate it. 2

      Theoretical argument · Significant · Open. On the record

    • Openings for airflow, power and optics weaken shielding in Side-channel suppression for isolated facilities

      Cankaya notes that keeping attenuation high while passing high-power airflow, cabling and optical links adds complexity beyond existing shielded-enclosure specifications. 2

      Theoretical argument · Significant · Open. On the record

    • Inspection assumptions may not hold in Side-channel suppression for isolated facilities

      The design's statistical argument assumes that visual or disassembly inspection catches every flaw that is present in a sampled unit. Cankaya is unsure whether destructive teardowns are defence-dominant or offence-dominant. 2

      Open question · Significant · Open. On the record

Open significant flaws
5 flaws in 3 mechanisms
  • Everything rests on the trusted setup in RAND secure inference data center (SIDC) design

    Reference measurements for model weights and reference data are established in a trusted setup phase. The report states that the system cannot detect compromise that happened before ingestion if the trusted setup itself is compromised. 1

    Theoretical argument · Significant · Open. On the record

  • Tolerance for numerical noise leaves a covert channel in Sampled inference recomputation

    Schemes that accept approximate matches can put an upper bound on an adversary's covert bandwidth, but they cannot close the channel. The weight-exfiltration detector cut exfiltratable information to under 0.5%, not to zero, on a 30-billion-parameter mixture-of-experts model under benign prompt traffic. Its authors called the channel's size under adversarial prompts an open empirical question. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token. Across six models, that cut the slowdown from 146–254 times under benign prompts to 60–118 times. The attack widens the exfiltration bound. It does not target the check that outputs match the declared model. 3 11 14

    Demonstrated attack · Significant · Open. On the record

    Related mechanism R3 Deterministic and bit-exact inference: Bit-exact inference would remove the numerical tolerance if exact replay can be deployed with the required weights and configuration. A pointer, not evidence that this flaw is mitigated. Add

  • Only recorded traffic is checked in Sampled inference recomputation

    Recomputation checks that recorded, declared workloads are correct. It cannot show that the record is complete. The published schemes do not cover hidden workloads run on the same compute, or substituted work. Rinberg et al. say their exfiltration-detection scheme cannot stand alone. 3 15

    Theoretical argument · Significant · Open. On the record

    Related mechanism R1 Network taps and certifiers: Taps copy and hash all traffic on the monitored links, which bears on whether the traffic record is complete. They do not show what else ran on the same chips. A pointer, not evidence that this flaw is mitigated. Add

  • Some inference optimizations are not covered in Sampled inference recomputation

    TOPLOC's authors state that it cannot detect speculative decoding in which a cheaper model does the decoding. They did not test whether it distinguishes types of key-value (KV) cache compression. DiFR was evaluated only on sampling from a single model. Its authors sketch an extension to one speculative-decoding algorithm but do not test it. 4 5

    Theoretical argument · Significant · Open. On the record

  • Remote memory narrows the timing margin in Timed challenge-response and memory-occupation challenges

    Data-centre remote memory access returns in about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview says verification of memory saturation depends on ruling out remote access by latency or physical disconnection. It adds that pre-staging data is ruled out only by unpredictable, capacity-filling challenges. 16

    Theoretical argument · Significant · Open. On the record

    Related mechanism R2 Bandwidth limits and compartmentalization: Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced. A pointer, not evidence that this flaw is mitigated. Add

Open minor flaws
3 mechanisms with minor findings
  • Security weakens over long operation in RAND secure inference data center (SIDC) design

    The authors claim that the facility can withstand attacks at the OC5 level for a five-year operational period. They expect its ability to withstand long OC5 campaigns to become less robust the longer the facility remains in operation. 1

    Theoretical argument · Minor · Open. On the record

  • Mixed hardware widens the honest baseline in Sampled inference recomputation

    When honest reference runs span different GPU types, the spread of benign scores grows. In DiFR's tests on Qwen3-30B-A3B, pooling A100 and H200 runs left Token-DiFR unable to separate the two smallest tested changes, a temperature of 1.1 instead of 1.0 and a simulated top-2 sampling bug, at the target false-positive rate, while cross-entropy separated them. Matched provider and verifier environments, or pooling that weights rare large deviations, restored detection. 4

    Open question · Minor · Open. On the record

  • Error rates not quantified in Timed challenge-response and memory-occupation challenges

    Monfared et al. show separable timing distributions but do not define thresholds or statistical tests, so false-positive and false-negative rates are not quantified. 18

    Open question · Minor · Open. On the record

Possible additions3 for open flaws · 3 for dependencies

Mechanisms on the map that are not in the proposal. Pointers, not recommendations.

    • Bears on the open significant flaw “Tolerance for numerical noise leaves a covert channel” in Sampled inference recomputation. Bit-exact inference would remove the numerical tolerance if exact replay can be deployed with the required weights and configuration.
    • Bears on the open significant flaw “Remote memory narrows the timing margin” in Timed challenge-response and memory-occupation challenges. Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced.
    • Timed challenge-response and memory-occupation challenges waits on it. Outside help, such as remote memory, must be excluded during challenges.
    • Bears on the open significant flaw “Only recorded traffic is checked” in Sampled inference recomputation. Taps copy and hash all traffic on the monitored links, which bears on whether the traffic record is complete. They do not show what else ran on the same chips.
    • Sampled inference recomputation waits on it. In tap-based retrofit designs, recording all inference traffic needs network taps and recomputation servers that can ingest it, in the worst case one recomputation-server network interface per inference front-end interface.
    • Side-channel suppression for isolated facilities depends on it.
Dependencies1 missing prerequisite · 12 blockers
Missing prerequisites
Blockers
12 blockers recorded
  • Side-channel suppression for isolated facilities
    • No prototype exists; RAND recommends prototyping key security features and integration now. Adversarial validation 1
    • The report describes internal integrity checks, audit logging and accreditation, but no way for a party outside the operator to verify the facility's properties. Access & governance 1
    • Human review of every prompt and response makes each request take three to five minutes, with the review steps as the rate-limiting factor. Performance & compatibility 1
    • Detailed design information is withheld from the public report and is to be evaluated privately with stakeholders, which limits independent public scrutiny. Access & governance 1
  • Sampled inference recomputation
    • In tap-based retrofit designs, recording all inference traffic needs network taps and recomputation servers that can ingest it, in the worst case one recomputation-server network interface per inference front-end interface. Coverage & hidden compute. Waits on Network taps and certifiers 10 17
    • In retrofit designs, the recomputation server must sit inside the prover's data centre, possibly under the prover's physical control, and still be protected from a compromised provider, which Amodo rates 'not on track'. Hardware trust 3 10
    • No independent red-team of a recomputation consistency check has been published (the one independent attack study targets the weight-exfiltration bound), and Amodo rates recomputation red-teaming 'not started'. Adversarial validation 10 11
    • Tolerance-based checks need calibration on trusted hardware and exact knowledge of the provider's sampling procedure, and in one prototype a sampling-implementation mismatch produced large spurious differences. Performance & compatibility 4 9
    • The verifier needs the model weights, so checking a closed-weights model requires a trusted, confidential recomputation environment, which the retrofit designs place inside the prover's facility. Privacy & leakage 4 15 16
  • Timed challenge-response and memory-occupation challenges
    • No network-level memory challenge across data-centre servers has been demonstrated. Adversarial validation 16
    • Challenges that fill memory displace workloads; filling a pod's volatile memory takes tens of minutes and SSDs take hours. Performance & compatibility 16 18
    • Outside help, such as remote memory, must be excluded during challenges. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization 16
What the verifier sees1 unspecified · 1 depend on design

From the family or selected implementation's record.

Model weights

Depends on the design for Sampled inference recomputation.

Not involved: Timed challenge-response and memory-occupation challenges.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Inputs and outputs

Depends on the design for Sampled inference recomputation.

Not involved: Timed challenge-response and memory-occupation challenges.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Exposure notes
Implementations10 systems
Side-channel suppression for isolated facilities
Sampled inference recomputation
Timed challenge-response and memory-occupation challenges
Sources25 cited
  1. Highly Secure Inference Data Centers: A Vertically Integrated Strategy for Security Engineering, S. F. Comer et al. (2026). Original
  2. Suppressing Side Channels in an Untrusted Data Center via Retrofitted Defenses, N. Cankaya (2026). Original
  3. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
  4. DiFR: Inference Verification Despite Nondeterminism, A. Karvonen et al. (2025). Original
  5. TOPLOC: A Locality Sensitive Hashing Scheme for Trustless Verifiable Inference, J. M. Ong et al. (2025). Original
  6. PrimeIntellect-ai/toploc (GitHub repository), Prime Intellect (2025). Original
  7. INTELLECT-2: A Reasoning Model Trained Through Globally Decentralized Reinforcement Learning, Prime Intellect Team et al. (2025). Original
  8. adamkarvonen/difr (GitHub repository), A. Karvonen (2025). Original
  9. Scaling Recomputation Inference Verification, Amodo Design (2026). Original
  10. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original
  11. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
  12. SYNTHETIC-2 Release: Four Million Collaboratively Generated Reasoning Traces, Prime Intellect (2025). Original
  13. An Inference Verification Prototype — Stage 1, Amodo Design (2026). Original
  14. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
  15. Example Schemes for Verifying High-Stakes AI Agreements, Amodo Design (2026). Original
  16. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
  17. Verification Plan, R. Dean (2026). Original
  18. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
  19. SAGE: Software-based Attestation for GPU Execution, A. Ivanov et al. (2023). Original
  20. SWATT: SoftWare-based ATTestation for Embedded Devices, A. Seshadri et al. (2004). Original
  21. Proofs of Space, S. Dziembowski et al. (2015). Original
  22. Secure Code Update for Embedded Devices via Proofs of Secure Erasure, D. Perito & G. Tsudik (2010). Original
  23. Software-Based Memory Erasure with Relaxed Isolation Requirements, S. Bursuc et al. (2024). Original
  24. On the Difficulty of Software-Based Attestation of Embedded Devices, C. Castelluccia et al. (2009). Original
  25. Refutation of "On the Difficulty of Software-Based Attestation of Embedded Devices", A. Perrig & L. van Doorn (2010). Original

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Filter mechanisms

Filters apply to mechanisms only. They describe the setting a proposal is for, and all are off by default. A mechanism that a filter rules out is flagged and does not count towards claim coverage. Selected implementations use their own record fields. A match means not excluded; conditional or unspecified exposure stays with a note. Passing a filter does not establish that the assumptions hold in a deployment.

All 25 mechanisms match.

Prover

How far can the party being checked be trusted?

The prover is the party being checked. Semi-trusted designs rely on part of its stack: usually the chip vendor's hardware root of trust, its firmware or counters, or its supply-chain records. Adversarial designs aim to hold even if it cheats wherever the checks allow, within their stated assumptions.

Keeps mechanisms whose threat model holds against at least this prover. Adversarial is the strongest assumption. Definitions

Verifier devices on site

May the verifier install its own hardware at the prover's sites?

Some mechanisms need a device the verifier owns or trusts at the prover's facility, such as a network tap, a bandwidth limiter or a sealed sensor. Choose Not allowed when the setting rules that out. Inspectors are not covered.

"Not allowed" removes mechanisms that need a retrofit device, such as a network tap or a sealed sensor. Definitions

Prover cooperation

How much must the prover take part?

Required: the prover takes part, for example by logging requests, producing proofs or opening records. Partial: some access, such as installing a device. Not required: works from outside, such as satellite imagery.

"Partial at most" removes mechanisms that need the prover's active participation. "Not required" keeps only those that work without it. Definitions

Chips

May the proposal depend on new chip designs?

New chip features take years to reach a deployed fleet and cover only chips made after they ship. Mechanisms that use shipping features, such as trusted execution environments or performance counters, stay.

"Existing chips only" removes mechanisms that need changes to future chip designs. Definitions

Minimum readiness

How mature must each mechanism be?

A level describes the public evidence for a mechanism's stated use, not its cost or feasibility. R3 can still have open critical flaws.

Keeps mechanisms whose readiness level is at least this one. Definitions

Attack testing

How hard has each mechanism been attacked in public?

The strongest published attempt to break the mechanism for its verification use: a security analysis, red-teaming by its developers or collaborators, or a red team independent of them.

Keeps mechanisms whose strongest published attack testing is at least this. Definitions

Keep hidden from the verifier

What must the verifier never see? Choose any.

Model weights: the checked model's parameters. Inputs and outputs: the requests a deployed model serves and its responses. Training data: what a model was trained on. Each mechanism's exposure is the editors' reading of its record: shown, depends on the design (kept, with a note), hidden, not involved, or unspecified for a selected implementation. Code and configuration are not covered yet.

Removes mechanisms that show the asset to the verifier. Conditional or unspecified exposure stays with a note and needs checking against the privacy requirement.

Claims

A claim is something one party wants to verify about another party's AI hardware or software. Each claim's number shows how the proposal addresses it.

  • Addressed. A mechanism in the proposal is aimed at this claim and is not excluded by the filters.
  • Partly addressed. Only supporting mechanisms, or mechanisms aimed at it that the filters exclude.
  • Unaddressed. No mechanism in the proposal addresses this claim.

Addressed means a mechanism in the proposal is aimed at the claim and is not excluded by your filters. It does not mean the claim is verified: check its assessed use, readiness, assumptions and open flaws.

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Mechanisms

A mechanism is a general technique for verifying claims. Its badge is its readiness level for its stated use. An optional implementation choice narrows its assumptions, assessed use and claim links to that record. Lines join it to the claims it addresses. Click a line for details.Under its name it lists the claims it is aimed at or supports.

  • Aimed at the claim: verifying it is a direct purpose of the mechanism.
  • Supports the claim: helps verify it without being aimed at it.
  • Faint: excluded by your filters, so it does not count towards claim coverage.

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Overview

One row per mechanism in the proposal. Every mark comes from that mechanism's record, as listed in the panels below; what the verifier sees is the editors' reading of the record's text. Flaw counts are per mechanism. Summary counts name mechanisms with open findings, not a sum of attacks. Choosing an implementation narrows each row to that record's assessed use; family findings remain as context.

What the verifier sees

For model weights, inputs and outputs, and training data. This is the editors' reading of each mechanism's record (its threat model, how it works and its limitations), not a field of the record. Shown: the verifier sees it. Depends: on the design or variant, or the verifier sees only samples. Hidden: the verifier sees only commitments, hashes, proofs or results. Not involved: the record does not handle it. Unspecified: the selected implementation has no asset-specific assessment here.

Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open flaw or a dependency. They are pointers, not recommendations: each brings its own readiness level and flaws, and none is claimed to close a flaw. Links from flaws are the editors' reading of the two records.

Start from a published design

Choosing a design loads the mechanisms its record realises or depends on. If the proposal has no claims yet, it also loads the claims that record says the design addresses.

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