Mechanism · Isolation & system architectures

Memory wiping and proofs of secure erasure

Overwriting all of a device's memory in a way a verifier can check, so that nothing from earlier, undeclared work survives the wipe.

Also called Proofs of secure erasure (PoSE); Periodic memory wipes; Forced memorization

R1Proposed

Summary

Memory wiping overwrites a device's memory in a way a verifier can check, so nothing from earlier work survives. In AI verification, periodic wipes would help show that only verified outputs carry forward. The technique builds on proofs of secure erasure: the device fills its memory with data derived from a verifier's seed, then answers timed questions about it. The theory is peer-reviewed. Scaling from erasure runs on CPUs, GPUs and disks, Amodo estimates about 43 minutes to wipe the memory of one GB200 tray and about 2.5 hours for an NVL72 rack's storage. As of September 2026 no end-to-end wipe with timed challenges has been published for data-centre hardware. The main obstacles are wipe time and memory the wipe cannot reach, such as drive-controller DRAM. The largest known weakness is that the guarantee depends on ruling out outside help during challenges, which fast data-centre networks make harder.

ReadinessR1Proposedlow confidence · rubric v1.0 · 2026-09-23

R1: the protocols are peer-reviewed and the AI use is proposed, but no public run covers the timed challenge phase on data-centre hardware.

Rubric assessment
  • R1 met: the AI 2040 plan proposes periodic memory wipes on inference units so that only verified outputs persist 1. Peer-reviewed and preprint protocols define proofs of secure erasure and their assumptions 2 3. The MIRI overview specifies filling memory with incompressible data and challenging random samples 4.
  • R2 not clearly met: Amodo has run a Bursuc-style erasure on a Raspberry Pi 5 and benchmarked label generation on H200 and H100 GPUs, CPUs and NVMe drives 5 6. Its public code for the GPU-accelerated disk-wiping path runs on realistic hardware 7. But the repository excludes "the verifier, the RAM and GPU-HBM session code" 7, the notes report fill throughput rather than timed challenge rounds 5 6, and the GB200 figures are estimates scaled from component measurements 5 6. Bursuc et al. simulated a 32 KB erasure on a desktop computer 3. The mechanism's implementations, AI 2040 inference-only verification stack and Low-trust AI compute verification system overview, are proposed architectures at R1.

Confidence is low because the public disk-wiping code on data-centre GPUs and drives could be read as meeting R2 in the hardware respect.

Gaps to the next level
  • A public end-to-end wipe of an accelerator server, covering fill and timed challenges by a separate verifier, for host memory, HBM and storage.
  • Coverage of memory the wipe cannot reach: drive-controller DRAM, firmware stores, NICs, DPUs and switches, and the algorithm's own working memory.
  • Adversarial evaluation in a data-centre setting, including remote-memory (RDMA) help during challenges.

How it works

Proofs of secure erasure (PoSE), introduced by Perito and Tsudik for low-cost embedded devices, rely on the bounded memory of such devices 2. A verifier confirms that a device has erased its memory by having it fill that memory with data the verifier can check 3. Perito and Tsudik found this "particularly well-suited" to secure code update and to secure memory or storage erasure 2.

A protocol has three phases 3:

  1. Fill. The prover fills its memory. In the simplest version the verifier sends random data; in graph-based versions it sends a short seed, and the device computes a large set of hash-chained labels from it 3.
  2. Challenge. The verifier asks for randomly chosen blocks, several times, and times each answer 3.
  3. Decide. The verifier accepts only if every answer is correct and arrived within the time bound 3.

The graph construction makes it slow to recompute any missing label, so a device that tried to keep other data must fail the deadline 3 5.

In AI verification, the AI 2040 plan proposes "periodic memory wiping on the inference units (which we think can be done through forced memorization)" 1. The MIRI overview describes the same step: incompressible data is loaded until the device is full, and then random samples are challenged 4. Amodo generates the fill on the device from a verifier seed, following Bursuc et al. 5.

What it establishes

Amodo describes the goal as a verifier ensuring "the prover has fully overwritten its memory, with no information persisted across the wipe" 5. Amodo says wipes help to verify the "completeness" of declared workloads 5. In the AI 2040 plan they help ensure that the only persisting results are verified inference outputs 1; see This compute runs inference, not training.

Wipes limit what can carry over between verification cycles, not what runs between them. The AI 2040 plan therefore pairs them with network taps and partial recomputation (Network taps and certifiers, Sampled inference recomputation) 1. Amodo notes that all stores must be wiped at the same time, because otherwise "an attacker could simply move the data between the disks" 5.

Threat model

  • Bounded memory. Perito and Tsudik assume bounded memory and a small read-only memory 2.
  • Distant helpers. Earlier software protocols assumed the device was isolated during the protocol 3. Bursuc et al. relax this: helpers may exist but must be far enough away that their round-trip times exceed the deadline 3.
  • Round-trip time. Amodo assumes a 1 ms round-trip time, "expected to be a safe overestimate" 5.
  • No remote memory. The MIRI overview says verification depends on ruling out remote memory access, "either via response latency or physical disconnection" 4.

Timed challenges are covered in Timed challenge-response and memory-occupation challenges.

Evidence

  • Protocols. The core protocols are formally analysed 2 3. Bursuc et al. ran their prototype on a standard desktop computer and simulated the erasure of 32 KB, which took 0.25 seconds 3.
  • First Amodo test. Amodo ran the algorithm on a Raspberry Pi 5, erasing its RAM and a connected SSD 5.
  • Amodo's July 2026 analysis. Scaling measured GPU and CPU throughputs, with an assumed 1 ms round-trip time, gave 2,565 seconds (43 minutes) for the RAM and HBM of a GB200 tray 5. Drive writes slowed sharply after about 12 GiB, so Amodo estimated over 24 hours for a GB200 system with 15 TB of storage 5. Challenge-phase calculations were still to come 5.
  • Amodo's September 2026 update. Amodo attributed the slowdown to consumer drives' fast write cache running out 6. Six GPUs wiping one fast drive reached 6 minutes 41 seconds per TB 6. Amodo now expects "~2.5 hours to wipe an NVL72 system's storage", using a B200 label rate estimated from its GPU benchmarks, and reports that erasure speed, not drive speed, is the bottleneck 6.
  • Public code. Amodo has published code for the disk-wiping path, which fills every sector of an NVMe drive with graph labels generated on NVIDIA GPUs 7. The repository excludes the verifier and the RAM and GPU-HBM session code 7.

Limitations

  • Unreachable memory. SSD controller DRAM sits on a private bus that host commands cannot access 6. Amodo's code notes that overwriting by logical block address cannot reach over-provisioned or remapped blocks either 7. The optimized algorithm's 25 GiB of working memory is "supposedly wiped but isn't attested" 6. Amodo lists many other stores in a GB200 system and asks how network-switch memory could be wiped 5.
  • Outside help. In data centres, remote memory round trips of about 1–2 µs compare with about 70–200 ns for local DRAM, which the MIRI overview puts at roughly a tenfold timing margin 4. Evasion by pre-staging data is closed only by unpredictable, capacity-filling challenges 4.
  • Downtime. Filling a pod's volatile memory takes tens of minutes, and SSDs take hours 4.
  • Residual gap. Memory between the erased region and full capacity could hold data 3. Bursuc et al. say that closing this gap needs future work 3.

Known flaws

Published flaws, with their severity, kind and status. How flaws are rated.

  • Memory the wipe cannot reachSignificantOpen questionOpen

    Amodo's inventory of a GB200 system lists many memory stores beyond GPU HBM and host DRAM. It notes that SSD controller DRAM sits on a private bus that host commands cannot read or write, and that its optimized algorithm leaves 25 GiB of HBM unattested. It also asks how switch memory could be wiped.

    Sources: [5] [6]
  • Outside help during challengesSignificantTheoretical argumentOpen

    Classic proofs of secure erasure assume the device is isolated during the protocol. Bursuc et al. relax this to a bound on how close a helper can be, enforced by round-trip times. In data centres, remote memory access has round trips of about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview therefore says verification depends on ruling out RDMA by latency or physical disconnection.

    Sources: [3] [4]
  • Gap between erased and total memoryMinorTheoretical argumentOpen

    Bursuc et al. note that memory left between the erased region and the device's full memory could hold data, and that their bounds are tighter only against a restricted adversary.

    Sources: [3]

Blockers

Technical detail

Show technical detail
  • Origin. Perito and Tsudik introduced proofs of secure erasure (PoSE) for embedded devices with bounded memory and a small ROM 2.
  • Bursuc et al.'s model. The adversary is a distant, memory-unbounded helper A0 and a local device A1 bounded to memory M. The protocol has an initialization phase (fill memory), r timed challenge-response rounds, and a verification phase that accepts only if the answers are correct and each round-trip time is at most Δ 3.
  • Variants. An unconditional variant fills memory with random bits sent by the verifier. A graph-based variant sends only a seed: the prover computes labels of a depth-robust graph with a hash function and stores the output labels, and a construction with in-place labelling needs only about the output size plus O(w) memory. A lightweight variant relaxes depth-robustness to a small constant for speed 3.
  • Prototype. Bursuc et al. ran their prototype on a standard desktop computer and simulated the erasure of 32 KB, which took 0.25 s; compiled for a 32-bit architecture, the program is 3.4 KB 3.
  • Amodo's implementation. It follows Bursuc et al.: node labels are L(n) = H(n ∥ L(p1) ∥ … ∥ L(pk)), only "robust" labels are stored and challengeable, and the scheme is secure if q < γ, where q is the number of hashes a cheater can compute within the round-trip time and γ is the minimum number of hashes needed to recompute a robust label 5.
  • Amodo's parameters and throughput. An assumed RTT of 1 ms; γ = 65,536 for host RAM and 32,768 for GPU HBM; Dual-AES-PRF on CPU and BLAKE3 on GPU. The measured throughputs, 126.3 MiB/s for 120 GB of RAM and 244.5 MiB/s for 140 GB of HBM, scale to 2,565 s for the memory sizes in a GB200 tray 5.
  • Disk path. A later optimization parallelized label generation across GPUs and reached 6 min 41 s per TB with 6 GPUs on one fast drive; it needs 25 GiB of working memory, which is left unattested if used on HBM 6. The NVL72 storage estimate assumes 30.72 TB of drives per tray and an estimated 840 MiB/s per B200 GPU, four GPUs per tray 6. Code for this path (CUDA graph labeller, multi-GPU disk-wipe benchmark with sample verification, wipe-time calculator) is public under the MIT licence 7.

Sources

  1. CR. Dean (2026). Verification Plan. AI 2040. Source recordSupports: periodic memory wipes on inference units via forced memorization; purpose · inference-only retrofitting proposal; verification overview
  2. AD. Perito & G. Tsudik (2010). Secure Code Update for Embedded Devices via Proofs of Secure Erasure. Computer Security – ESORICS 2010, LNCS 6345, pp. 643–662. Source recordSupports: origin of proofs of secure erasure; bounded-memory model; applications · abstract
  3. AS. Bursuc et al. (2024). Software-Based Memory Erasure with Relaxed Isolation Requirements. 2024 IEEE 37th Computer Security Foundations Symposium (CSF 2024). Source recordSupports: PoSE with relaxed isolation; adversary model; graph constructions; prototype; stated gap · §1–§8; implementation section; conclusion
  4. BN. Cankaya (2026). A System Overview for Near-Term, Low-Trust AI Compute Verification. Machine Intelligence Research Institute. Source recordSupports: memory-occupation fill and challenge; fill times; RDMA caveat and latencies · §5.1.2
  5. CAmodo Design (2026). Memory Wipes - Performance Analysis. Amodo Design. Source recordSupports: PoSE implementation, security condition, parameters, measured throughputs, GB200 estimates, memory inventory, open questions · whole note (corrected version)
  6. CAmodo Design (2026). Improving Disk Wiping Speed for Memory Wipes. Amodo Design. Source recordSupports: multi-GPU label generation, per-TB wipe rate, NVL72 storage estimate and its assumptions, SSD DRAM and scratch limits · whole note
  7. BAmodo Design (2026). Amodo-Design/PoSE-Memory-Wiping (GitHub repository). GitHub. Source recordSupports: public disk-wiping code; scope and exclusions; LBA overwrite limits · README

M-0015JSONSource-checked 2026-09-23 · changed 2026-09-24Suggest a correction

Drafted with AI assistance and checked against the cited sources by an independent verifier. Expert review pending. Readiness assessed by the AI draft on 2026-09-23. How records are made.