Organization · Academic
Hardware AI Governance Lab
A University of Oxford lab, hosted by the Oxford Martin AI Governance Initiative, that studies how computer hardware can support AI governance and international coordination.
aigi.ox.ac.uk/hardware-ai-governance-lab · also called HAIGL; Oxford Hardware AI Governance Lab
The Hardware AI Governance Lab (HAIGL) is an interdisciplinary initiative at the University of Oxford, hosted by the Oxford Martin AI Governance Initiative (AIGI) 1. Its co-directors are Amro Awad and Robert Trager, and Ben Harack is its co-founder and research lead 1.
The lab states that it treats hardware architecture as a foundational layer for embedding oversight, verification and control mechanisms 1. It names three aims:
- It aims to turn high-level governance concepts into hardware design proposals, and then into early-stage feasibility prototypes 1.
- It explores ways to verify how AI systems behave, and whether some governance constraints can be enforced directly in hardware 1.
- It studies how agreements between states could be structured and implemented when the parties have limited trust in each other 1.
The lab expects to release its first hardware governance design profile in late 2026 1. It lists two 2026 papers among its publications 1:
- A design for fingerprinting all of an AI cluster's I/O without processors that both parties must trust. It aims to make it infeasible to covertly exfiltrate the results of undisclosed workloads through the tapped links 2. Its first author lists the lab as an affiliation 2. See Network taps and certifiers and Low-trust AI compute verification system overview.
- A survey of verifiable semiconductor manufacturing that develops a threat model spanning chip design through manufacturing. It argues that defence in depth is required, with assurance tiered by chip criticality, and that neutral third-party verification authorities can help overcome industry opacity 3. Two of its four authors list the lab as an affiliation 3.
Mechanisms
Mechanisms this organization has designed, built, evaluated or supplied.
- Devices on a cluster's network links that copy and hash all traffic, so a verifier can later check sampled records against declared work.
Publications
Sources this organization authored or published.
- BN. Cankaya et al. (2026). Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors. arXiv. RecordCited by Network taps and certifiers; Low-trust AI compute verification system overview; Hardware AI Governance Lab
- BHardware AI Governance Lab. Oxford Martin AI Governance Initiative. RecordCited by Hardware AI Governance Lab; Oxford Martin AI Governance Initiative
- BA. Ilhan et al. (2026). Verifiable Semiconductor Manufacturing. Oxford Martin AI Governance Initiative. RecordCited by Hardware AI Governance Lab
Mentioned in
Sources
- BHardware AI Governance Lab. Oxford Martin AI Governance Initiative. Source recordSupports: hosted by AIGI; co-directors and research lead; research focus and aims; first design profile expected in late 2026; lists S-1300 and S-1704 among its publications
- BN. Cankaya et al. (2026). Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors. arXiv. Source recordSupports: cluster I/O fingerprinting design and its aim; first author affiliated with the lab
- BA. Ilhan et al. (2026). Verifiable Semiconductor Manufacturing. Oxford Martin AI Governance Initiative. Source recordSupports: chip manufacturing threat model, defence in depth and tiered assurance; two authors affiliated with the lab