Proposal Explorer

Add claims to see which ones the mechanisms address.

In production

• R3 Model identity attestation for showing users that a service runs the declared model weights
• R3 Deterministic and bit-exact inference for reproducing open-model inference from receipts in Gensyn's information-market service

Built for an adversarial prover

Deterministic and bit-exact inference

No new hardware needed

Model identity attestation, Chip registries and manufacturing records and Deterministic and bit-exact inference

Flaws since mitigated

• Launch-state attestation does not by itself cover weights loaded later in Model identity attestation ^{1 13}

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Model identity attestation: Independent red-team
• Chip registries and manufacturing records: Analysis
• Deterministic and bit-exact inference: Analysis

Open critical flaws

• Underlying attestation can be forged or relayed in Model identity attestation

  Critical for the enclave route against an operator with physical access to affected hardware, or control of an unpatched SEV-SNP hypervisor. It does not apply to the recomputation route. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary.

  The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. ^{2 4 8 10 11 12}

  Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

  Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

  Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this flaw is mitigated. Add

Open significant flaws

6 flaws in 3 mechanisms

• For private models, a user can confirm consistency but not content in Model identity attestation

  When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy. ^{1 14}

  Open question · Significant · Open. On the record

• Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel in Model identity attestation

  The recomputation variant assumes that every input, output and seed is logged correctly, and that the attacker can neither predict nor manipulate which messages are sampled for verification. Legitimate nondeterminism concentrates at a few token positions, and slow leaks within the tolerated slack remain possible. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token, reducing the exfiltration slowdown from 146–254 times under benign prompts to 60–118 times. The attack targets the exfiltration bound, not the check that outputs match the declared model. ^{3 9}

  Demonstrated attack · Significant · Open. On the record

  Related mechanism R1 Network taps and certifiers: Taps are proposed to copy and hash traffic on the monitored links, reducing reliance on the prover's own log. This still depends on the monitored boundary and trusted capture. A pointer, not evidence that this flaw is mitigated. Add

  Related mechanism R3 Deterministic and bit-exact inference: Bit-exact inference would remove the numerical tolerance that leaves this channel. A pointer, not evidence that this flaw is mitigated. In the proposal.

• Records cover only chips that were recorded in Chip registries and manufacturing records

  A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. ^{17 19}

  Theoretical argument · Significant · Open. On the record

  Related mechanism R1 Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this flaw is mitigated. Add

• Documents and serial numbers can be forged in Chip registries and manufacturing records

  Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. ¹⁶

  Theoretical argument · Significant · Open. On the record

• Insiders could alter records before they are fixed in Chip registries and manufacturing records

  Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. ¹⁷

  Theoretical argument · Significant · Open. On the record

• Cross-hardware replay relies on reverse-engineered, closed behaviour in Deterministic and bit-exact inference

  Emulating one GPU's rounding on another requires reverse-engineering tensor-core arithmetic and modelling proprietary kernel choices. Hawkeye covers a subset of NVIDIA architectures and states that attention and other higher-level operations need further reverse engineering. For the bit-exact emulator, a proprietary Hopper kernel family is an open edge case. ^{20 22}

  Open question · Significant · Open. On the record

Open minor flaws

1 mechanism with minor findings

• Some kernels remain genuinely nondeterministic in Deterministic and bit-exact inference

  The bit-exact work separates kernels that are deterministic but not batch-invariant from truly nondeterministic ones that use atomic functions. Some integer de-quantization kernels use atomic additions and remain nondeterministic, so exact replay needs backends that avoid them. ²⁰

  Open question · Minor · Open. On the record

Not yet demonstrated

R1 Chip registries and manufacturing records

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R1 Network taps and certifiers Add
  • Bears on the open significant flaw “Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel” in Model identity attestation. Taps are proposed to copy and hash traffic on the monitored links, reducing reliance on the prover's own log. This still depends on the monitored boundary and trusted capture.
• R1 Remote detection of data centres Add
  • Bears on the open significant flaw “Records cover only chips that were recorded” in Chip registries and manufacturing records. Looks for large data centres that were never declared, which a registry cannot show.
• R3 TEE remote attestation for AI workloads Add
  • Model identity attestation waits on it. Attestation that resists physical attackers, for the enclave variant.
• R1 Hardware-enabled guarantees (flexHEG) and guarantee processors Add

  Excluded by filters: needs new chips

  • Bears on the open critical flaw “Underlying attestation can be forged or relayed” in Model identity attestation. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.

Blockers

10 blockers recorded

• Model identity attestation
  • Attestation that resists physical attackers, for the enclave variant. Hardware trust. Waits on TEE remote attestation for AI workloads ⁸
  • Numerical nondeterminism limits how tightly recomputation can pin down the model and sampling. Protocol soundness. Waits on Deterministic and bit-exact inference ³
  • The recomputation variant needs the verifier to hold the declared weights. Access & governance ³
• Chip registries and manufacturing records
  • No AI chip registry operates, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance ^{15 16}
  • Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust ^{15 16 17}
  • Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute ^{17 19}
• Deterministic and bit-exact inference
  • Batch-invariant kernels cost throughput: in Thinking Machines' Qwen3-8B test, an improved deterministic build took 42 s against 26 s for vLLM's default, and SGLang reports an average 34.35% slowdown on its FlashInfer and FlashAttention 3 backends. Performance & compatibility ^{21 23}
  • Coverage is incomplete: the bit-exact emulator targets dense blocks on NVIDIA GPUs and excludes mixture-of-experts inference and training, and vLLM's batch-invariant mode is in beta, with open work on AMD hardware and speculative decoding. Performance & compatibility ^{20 24 31}
  • Amodo's status page for the AI 2040 verification plan rates a reproducible inference stack for that plan as 'not started'. Performance & compatibility ³²
  • Exact replay requires the prover to disclose weights, software versions, parallelism and batch sizes to whoever recomputes. Privacy & leakage ^{20 30}

From the family or selected implementation's record. ?

Model weights

Depends on the design for Model identity attestation and Deterministic and bit-exact inference.

Not involved: Chip registries and manufacturing records.

Inputs and outputs

Depends on the design for Model identity attestation and Deterministic and bit-exact inference.

Not involved: Chip registries and manufacturing records.

Training data

Not involved: Model identity attestation, Chip registries and manufacturing records and Deterministic and bit-exact inference.

Model identity attestation

• R2 Attestable Audits Research prototype, University of Cambridge
• R2 PAL*M Research prototype, University of Waterloo
• R3 Tinfoil model identity (Modelwrap) Product, Tinfoil

Chip registries and manufacturing records

None on the map

Deterministic and bit-exact inference

• R2 Batch-invariant inference kernels (Thinking Machines) Open-source project, Thinking Machines Lab
• R3 Verde and RepOps (Gensyn) Product, Gensyn
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute

1. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
2. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
3. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
4. A primer on secure enclaves, Tinfoil (2026). Original
5. Backend infrastructure, Tinfoil (2026). Original
6. How verification works in Tinfoil, Tinfoil (2026). Original
7. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). Original
8. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
9. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
10. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
11. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
12. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
13. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
14. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original
15. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
16. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
17. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
18. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
19. Covert AI Projects, B. Halstead & T. Larsen (2026). Original
20. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
21. Defeating Nondeterminism in LLM Inference, H. He & Thinking Machines Lab (2025). Original
22. Hawkeye: Reproducing GPU-Level Non-Determinism, E. Badash et al. (2026). Original
23. Towards Deterministic Inference in SGLang and Reproducible RL Training, The SGLang Team (2025). Original
24. Batch Invariance (vLLM documentation), vLLM project (2026). Original
25. gensyn-ai/ree: Gensyn Reproducible Execution Environment (GitHub repository), Gensyn (2026). Original
26. EigenCloud Brings Verifiable AI to Mass Market with EigenAI and EigenCompute Launches, EigenCloud (2025). Original
27. Building Delphi: Pricing, Settlement, and Agentic Trading, D. Jedamski (2026). Original
28. Reproducible Execution Environment (REE) (Gensyn documentation), Gensyn (2026). Original
29. What is Delphi? (Delphi documentation), Gensyn (2026). Original
30. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
31. [Feature]: Batch Invariant Feature and Performance Optimization (vLLM issue #27433), vLLM project contributors (2025). Original
32. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original