Mechanism · On-chip & hardware-enabled

Hardware-enabled guarantees (flexHEG) and guarantee processors

Proposed chip add-ons, a guarantee processor inside a tamper-protected enclosure, that would check and enforce agreed rules on how AI accelerators are used.

Also called flexHEG; Flexible hardware-enabled guarantees; Guarantee processor; Interlock; Hardware-enabled governance mechanisms (HEMs); On-chip governance mechanisms

R1Proposed

Summary

Hardware-enabled governance mechanisms (HEMs) are proposed chip features that would let a verifier check, or the chip itself enforce, rules about how AI compute is used. The flexHEG proposal pairs an open, auditable guarantee processor, which sees all data and instructions going to and from an accelerator, with a secure enclosure that reveals or responds to tampering. Rule changes, such as to a cap on training compute, could require approval from several parties. RAND and CNAS describe related designs, such as offline licensing. All are designs; the one prototype mentioned is unpublished. The main obstacles are physical security against state attackers, chipmaker cooperation, and international trust in chip design and manufacturing. The authors estimate that integrated hardware would take 3.7–7.9 years from the start of chipmaker work to displace other accelerators at the frontier. Whether a use is malicious cannot be checked on the chip.

ReadinessR1Proposedmedium confidence · rubric v1.0 · 2026-09-23

R1. The design is detailed, but nothing has been built or tested in public.

Rubric assessment
  • R1 met: the flexHEG series sets out the components, the claims that could be verified or enforced, the update governance and a threat model that includes state-level adversaries 1 2 4. RAND and CNAS describe related HEM designs and their threats 5 6.
  • R2 not met. As of September 2026 no public implementation or reproducible end-to-end results have been published, and no Implementation record realises this mechanism. Part II mentions that "an existing FlexHEG prototype" uses high-resolution power measurements, but gives no details or results 2. Claimed results that are not public do not count. Because that prototype could not be checked, confidence is medium rather than high.
Gaps to the next level
  • A public prototype of a guarantee processor or Interlock on a real accelerator data path, with published end-to-end results.
  • A secure enclosure evaluated against invasive physical attacks, with published cost-to-circumvent estimates.
  • A specified ruleset language and a multi-party update protocol implemented and analysed.
  • Chipmaker engagement, needed for integrated designs.

How it works

RAND defines hardware-enabled governance mechanisms (HEMs) as controls built into AI hardware that enable "enforcement and compliance verification" of policies 5. It analyses two designs 5:

  • Offline licensing lets a GPU run a set amount of work under a renewable license, then refuse or slow further work.
  • The fixed set limits high-bandwidth links to a small pod of pre-authorized chips.

CNAS proposes a hardened security module that enforces valid firmware and up-to-date operating licenses and supports remote attestation. It would be rolled out in stages, from firmware changes to tamper-evident and then tamper-proof hardware 6. An interdisciplinary workshop report by O'Gara et al. discusses HEMs for four uses: verifiable AI training and inference, verifiable cluster configuration, location verification and offline licensing 7.

flexHEG (flexible hardware-enabled guarantees) combines two components 1:

  • Guarantee processor: "an open-source, standardized, general-purpose processor that sits between the AI chip and the rest of the world". It can see all information and instructions going to and from the chip 1.
  • Secure enclosure: it houses the chip and the guarantee processor. If tampering is detected, secrets are wiped 1.

When the guarantee processor sits directly on the data path, the design is called an Interlock. As the only way in, it can monitor or control the flow and encrypt data leaving the enclosure 2. The rules it applies form a ruleset, which anyone from the chip's owner alone up to "a quorum of states" might set 1. Changes could require k-of-n approval, and periodic licenses could force devices to stay current 2.

Part II of the flexHEG series describes a range of implementations 2:

  • Integrated hardware, built into the accelerator by its manufacturer.
  • Retrofits, such as modified firmware or a replacement network interface card acting as the Interlock.
  • TEE-backed software, which Part II judges relatively fast to deploy but probably not secure against sophisticated actors with unrestricted physical access.

Part III contrasts two kinds of agreement. In verification-based agreements, states detect violations and retaliate. In ruleset-based agreements, the devices enforce the rules and no state can rewrite them alone 4.

What it establishes

The authors list claims flexHEG could support 1:

  • the total compute used to train a model;
  • whether a model's score on an automated test stayed below, or rose above, an agreed level;
  • deployment only to approved devices;
  • a chip's approximate location;
  • which architectures and training techniques were used.

A guarantee processor could also block any operation that would push a training run past a threshold 1.

It cannot establish:

  • intent or downstream misuse, which is not observable on the chip 1;
  • whether a network is the whole system or one expert in a larger one 1;
  • a true FLOP count if earlier results are hidden in external inputs 2;
  • anything about compute without flexHEG hardware 1 4.

Fully automatic, on-device compliance checking "appears unlikely to be feasible" 1. Part III therefore discusses compromises that combine enforced rules with verification 4.

Threat model

In international use, "the primary attackers ... are the participating states themselves" 4. Devices would need to be open source, auditable and "robust to tampering even from state-level adversaries" 1. CNAS stresses that existing features "need to be hardened" before adversarial use 6.

RAND defines three kinds of threat actor: unsubsidized commercial, state-subsidized commercial, and state. It groups attacks into four classes 5:

  • non-invasive, for example side channels;
  • semi-invasive, such as fault injection;
  • fully invasive, such as focused ion beams and electron microscopy;
  • non-physical, including design theft and cryptographic, firmware, supply-chain and resource-pooling attacks.

The design also assumes a trustworthy supply chain. Part III proposes manufacturing equipment locked to standard designs, independent testing, camera oversight, tamper-evident shipping, and extensive testing and detailed physical imaging of a random sample of finished devices 4.

Evidence

  • Design reports. RAND and CNAS published design and analysis reports in 2024 5 6. The three flexHEG parts followed in 2025, commissioned by ARIA 1 2 4.
  • Timelines. CNAS estimates that the needed hardware security could take as little as 18 months, and up to 4 years, of technical effort by leading firms 6. Part II estimates 3.7–7.9 years for integrated flexHEG to displace other accelerators at the frontier, counted from when a manufacturer starts work. It argues that to reach its full potential, flexHEG would likely need to be deployed at scale "by 2027 or sooner" 2.
  • Prototype. Part II says that "an existing FlexHEG prototype uses high resolution power measurements", with no further detail 2.
  • Related work. Part II notes TEE-based efforts by Mithril Security and EQTY Lab 2.
  • Open questions. O'Gara et al. ask how to verify license authenticity at scale and how to attest the integrity of fixed-set pods remotely 7.

Limitations

  • Enclosures. The authors write that nation-state attackers "can likely compromise the best current secure enclosures" 2.
  • Retrofits. Designs that rely on Secure Boot are exposed to voltage glitching and probing 2.
  • Supply chain. Diversion and backdoors are open problems 2 4.
  • Evaluations. Making capability evaluations robust to models trained to underperform is "a very difficult open problem" 1.
  • Algorithmic efficiency. Gains lower the compute needed for a given capability over time 4.

Physical protection is covered in Tamper evidence for verifier devices, interconnect limits in Bandwidth limits and compartmentalization and throttling in Hardware performance throttling and licensing.

Known flaws

Published flaws, with their severity, kind and status. How flaws are rated.

  • State attackers can likely defeat current secure enclosuresSignificantTheoretical argumentOpen

    The flexHEG authors write that "nation-state attackers can likely compromise the best current secure enclosures", and that the marginal cost of circumvention per device is hard to estimate 2. RAND similarly judges that anti-tamper measures "would not be insurmountable for a determined and well-resourced adversary", although they raise costs and can reveal tampering 5.

  • Firmware-only retrofits rely on Secure Boot, which fault injection can bypassSignificantTheoretical argumentOpen

    Part II notes that the most common attack on Secure Boot replaces the firmware and applies a voltage glitch while the signature is being checked. It also notes that sophisticated actors may use microprobing or laser voltage probing to read key registers 2.

  • Many important rules cannot be checked on-chipSignificantTheoretical argumentOpen

    Malicious intent "is not a technical property observable on-chip", and misuse depends on what is done with a computation's results 1. A guarantee processor cannot easily tell whether a network is the whole system or one expert in a mixture-of-experts system 1. Part III judges that a fully local ruleset "may not be entirely feasible" for the same reason 4.

  • FLOP accounting can be laundered through external dataSignificantTheoretical argumentOpen

    Results of earlier or parallel workloads could be hidden in the "external data" fed to a device, which would falsify the total FLOP count unless the inputs are explained or time delays are imposed 2.

  • Supply-chain diversion and hidden backdoorsSignificantOpen questionOpen

    Components could be diverted before a guarantee processor is added, and backdoors could be introduced during design or manufacturing. Open-source designs and physical scans of randomly selected chips are proposed as countermeasures 2. Part III proposes international oversight of production and extensive testing of a random sample of finished devices 4.

  • Coverage stops at flexHEG-equipped chipsSignificantOpen questionOpen

    Motivated actors will always be able to use some compute that is not flexHEG-equipped 1. Recalling existing consumer GPUs would likely be impractical, and reaching perfect coverage, or conclusively proving that no secret government data centres exist, would be "practically quite difficult" 4.

Blockers

  • Integrated flexHEG needs substantial help from the accelerator manufacturer, and the authors estimate 3.7–7.9 years, from when the manufacturer starts work, for such hardware to displace other accelerators in frontier development.

    Access & governance[2]
  • State-level attackers who hold the hardware can likely compromise the best current secure enclosures.

  • Rival states would need to trust the design and manufacture of guarantee processors and enclosures, for example through open design, redundant processors from each side or oversight of production.

    Hardware trust[4][1]
  • Restricting future rule updates would need a formal language for rules, which the authors judge most likely infeasible for early flexHEG versions.

    Protocol soundness[1]
  • Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities.

Technical detail

Show technical detail
  • Interlock. A flexHEG component on the data path is called an Interlock. As the only path for data and instructions into the accelerator, it could monitor or control that flow and encrypt what leaves the enclosure. The candidate points are HBM, NVLink, PCIe and the cluster NIC 2.
  • Encryption cost. Part II roughly estimates that encrypting all NVLink traffic with AES-256-GCM would take about 3% of computing power, energy or board space, and encrypting all HBM traffic about 11% of power 2.
  • Checking and logging. Part II estimates that for a guarantee processor to double-check one streaming multiprocessor (SM) of a Blackwell chip would take roughly 1/192 of the chip's compute, assuming 192 SMs per chip 2. NVIDIA states that the Blackwell GPUs in its HGX B200 system normally have 148 SMs 3. Storing a FLOP log for 1M unique sources, such as a very large cluster, would take roughly 30 MB 2.
  • Updates. An update, or the lack of one, could require approval by k of n parties. Periodic licenses could specify a minimum firmware version, and signatures should ideally be quantum-resistant 2. A guarantee processor could be required to install a firmware update regularly, for example every three months, or it would block the chip 1.
  • Enclosure. Tamper evidence is sufficient for verification, while guarantees about future use need tamper response. Options include capacitor discharge or antifuses that disable the chip, PUF-derived keys, and sensors for radiation, voltage glitching, lasers and temperature 2.
  • Manufacturing oversight. Part III proposes extensive testing of a random sample, for example 1/1000 of finished devices, which would give a 63% chance of catching a batch of 1000 compromised devices at that stage 4.
  • RAND designs. An offline license might authorize 10^18 operations before the GPU falls back to 1% performance. A "fixed set" restricts high-bandwidth links to pre-authorized pods of fewer than 65 chips 5.

Sources

  1. BJ. Petrie et al. (2025). Flexible Hardware-Enabled Guarantees for AI Compute. arXiv. Source recordSupports: flexHEG definition, components, verifiable claims, rulesets, update restriction, limitations, relation to confidential computing · Executive Summary; Conceptual Overview; Appendix A-B
  2. BJ. Petrie & O. Aarne (2025). Technical Options for Flexible Hardware-Enabled Guarantees. arXiv. Source recordSupports: Interlock, secure enclosure, integration options, update authorization, overhead estimates (including the 1/192 SM estimate and its 192-SM assumption), timelines, prototype mention, attacks · sections on Interlock-Based Design, Secure Enclosure, Potential Accelerator Modifications
  3. BS. Nassernia (2025). Boost GPU Memory Performance with No Code Changes Using NVIDIA CUDA MPS. NVIDIA Technical Blog. Source recordSupports: NVIDIA states that the Blackwell GPUs in an HGX B200 system normally have 148 SMs · MLOPart section
  4. BO. Aarne & J. Petrie (2025). International Security Applications of Flexible Hardware-Enabled Guarantees. arXiv. Source recordSupports: verification- vs ruleset-based agreements, states as primary attackers, redundant processors, manufacturing oversight and sampling, coverage limits, algorithmic efficiency · Creating an Internationally Trustworthy FlexHEG Ecosystem; Overseeing Production
  5. BG. Kulp et al. (2024). Hardware-Enabled Governance Mechanisms: Developing Technical Solutions to Exempt Items Otherwise Classified Under Export Control Classification Numbers 3A090 and 4A090. RAND Corporation. Source recordSupports: HEM definition, offline licensing and fixed set, threat actor tiers, attack classes, anti-tamper limits · pp. viii-x, 4, 19-27
  6. BO. Aarne et al. (2024). Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing. Center for a New American Security. Source recordSupports: on-chip governance with existing features, hardening need, 18 months to 4 years estimate · Key findings
  7. BA. O'Gara et al. (2025). Hardware-Enabled Mechanisms for Verifying Responsible AI Development. arXiv. Source recordSupports: workshop agenda on HEMs (four uses) and open questions on licensing and pod attestation · §2; §2.3.4, §2.5.4

M-0009JSONSource-checked 2026-09-23 · changed 2026-09-24Suggest a correction

Drafted with AI assistance and checked against the cited sources by an independent verifier. Expert review pending. Readiness assessed by the AI draft on 2026-09-23. How records are made.