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Chip location verification and Deterministic and bit-exact inference

No new hardware needed

Chip location verification

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Chip location verification: Analysis
• Deterministic and bit-exact inference, Low-trust AI compute verification system overview: Analysis

Family findings

• Deterministic and bit-exact inference

  Context for Low-trust AI compute verification system overview. These findings concern the family or other implementations; applicability must be checked against their stated scope.

  • Some kernels remain genuinely nondeterministic in Deterministic and bit-exact inference

    The bit-exact work separates kernels that are deterministic but not batch-invariant from truly nondeterministic ones that use atomic functions. Some integer de-quantization kernels use atomic additions and remain nondeterministic, so exact replay needs backends that avoid them. ¹⁰

    Open question · Minor · Open. On the record

  • Cross-hardware replay relies on reverse-engineered, closed behaviour in Deterministic and bit-exact inference

    Emulating one GPU's rounding on another requires reverse-engineering tensor-core arithmetic and modelling proprietary kernel choices. Hawkeye covers a subset of NVIDIA architectures and states that attention and other higher-level operations need further reverse engineering. For the bit-exact emulator, a proprietary Hopper kernel family is an open edge case. ^{10 11}

    Open question · Significant · Open. On the record

Open significant flaws

6 flaws in 2 mechanisms

• Extracting a chip's key lets another device answer for it in Chip location verification

  Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM. ^{1 6}

  Theoretical argument · Significant · Open. On the record

• Added delay can shift an estimated position in Chip location verification

  Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location. ^{1 4}

  Demonstrated attack · Significant · Open. On the record

• Faster-than-assumed network paths in Chip location verification

  Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often. ^{1 4}

  Theoretical argument · Significant · Open. On the record

• Compromised landmarks can falsify measurements in Chip location verification

  A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators. ^{1 4 5}

  Theoretical argument · Significant · Open. On the record

• Mismatches cannot be attributed to cheating or error in Low-trust AI compute verification system overview

  A failed hash or replay does not show whether it came from an evasion attempt, a random bit flip or an evaluation error. The author notes that if detected anomalies can plausibly be waved off as malfunctions, deterrence becomes less effective, so the parties need an agreed escalation procedure that ends in attribution. ⁸

  Theoretical argument · Significant · Open. On the record

• Inspector agents may be manipulable in Low-trust AI compute verification system overview

  Automated compliance screening with LLM-based inspector agents must resist prompt-injection attacks. Adversarially trained systems might hide malicious actions with steganography, which makes backdoor detection an open problem. ⁸

  Open question · Significant · Open. On the record

Open minor flaws

1 mechanism with minor findings

• Deliberate faults leak a bit each in Low-trust AI compute verification system overview

  A malicious device can leak one bit by deliberately outputting a wrong result, which blocks a disclosure when the cross-comparison fails. The design therefore needs a pre-agreed budget of tolerated faults. ⁸

  Theoretical argument · Minor · Open. On the record

Not yet demonstrated

R1 Chip location verification and R1 Deterministic and bit-exact inference

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R2 Tamper evidence for verifier devices Add
  • Deterministic and bit-exact inference waits on it. Tamper-evident, rapidly mass-manufacturable and retrofittable enclosures for side-channel defence are an open research question, and physical security against covert communication in every monitored data centre is challenging.
• R2 Timed challenge-response and memory-occupation challenges Add
  • Deterministic and bit-exact inference waits on it. Distinguishing one server's DRAM contents from another's by challenge-response timing, and a general challenge-response protocol for diverse data types, are open.
• R1 Network taps and certifiers Add
  • Deterministic and bit-exact inference waits on it. Empirical feasibility of passive optical splitting at 53–112 GBaud under realistic conditions is an open question.
• R1 Side-channel suppression for isolated facilities Add
  • Deterministic and bit-exact inference waits on it. A mass-manufacturable, good-enough side-channel defence, particularly power-line filtering, has not been constructed or red-teamed.
• R3 TEE remote attestation for AI workloads Add
  • Chip location verification depends on it.

Missing prerequisites

• R3 TEE remote attestation for AI workloads needed by Chip location verification Add
• R1 Network taps and certifiers needed by Deterministic and bit-exact inference Add

Blockers

10 blockers recorded

• Chip location verification
  • No public code or reproducible end-to-end location results are available for the reported H100 prototype. Adversarial validation ^{2 3}
  • Per-chip keys must be provisioned and protected against extraction; hardware-integrated, tamper-resistant versions still need R&D. Hardware trust ^{1 6 12}
  • The time limit forces a trade-off: a limit at the speed of light in fibre can be beaten by faster links, while one at the vacuum speed of light makes honest chips fail often. Protocol soundness ¹
  • A trusted landmark network must be built and secured, and who should operate it, under what oversight, is unsettled. Access & governance ^{1 4}
• Deterministic and bit-exact inference
  • Empirical feasibility of passive optical splitting at 53–112 GBaud under realistic conditions is an open question. Performance & compatibility. Waits on Network taps and certifiers ⁸
  • Exact replay needs complete hardware and software metadata, and the tolerable slowdown from emulation is an open question. Performance & compatibility. Waits on Deterministic and bit-exact inference ⁸
  • Tamper-evident, rapidly mass-manufacturable and retrofittable enclosures for side-channel defence are an open research question, and physical security against covert communication in every monitored data centre is challenging. Hardware trust. Waits on Tamper evidence for verifier devices ⁸
  • A mass-manufacturable, good-enough side-channel defence, particularly power-line filtering, has not been constructed or red-teamed. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ⁸
  • Distinguishing one server's DRAM contents from another's by challenge-response timing, and a general challenge-response protocol for diverse data types, are open. Coverage & hidden compute. Waits on Timed challenge-response and memory-occupation challenges ⁸
  • The threat model is under-developed and needs input from cybersecurity and AI threat-modelling experts. Adversarial validation ⁸

From the family or selected implementation's record. ?

Model weights

Not involved: Chip location verification.

Unspecified for Deterministic and bit-exact inference. Check the implementation record.

Inputs and outputs

Not involved: Chip location verification.

Unspecified for Deterministic and bit-exact inference. Check the implementation record.

Training data

Not involved: Chip location verification.

Unspecified for Deterministic and bit-exact inference. Check the implementation record.

Chip location verification

• R1 Lucid sovereignty (location) certificates Standard, Lucid Computing

Deterministic and bit-exact inference

• R2 Batch-invariant inference kernels (Thinking Machines) Open-source project, Thinking Machines Lab
• R3 Verde and RepOps (Gensyn) Product, Gensyn
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute

1. Location Verification for AI Chips, A. Brass & O. Aarne (2024). Original
2. Location Verification for AI Chips (issue brief), A. Brass (2025). Original
3. Ping-based Location, Ulyssean (2025). Original
4. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
5. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). Original
6. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). Original
7. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
8. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
9. Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors, N. Cankaya et al. (2026). Original
10. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
11. Hawkeye: Reproducing GPU-Level Non-Determinism, E. Badash et al. (2026). Original
12. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original