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A verification proposal from the AI Verification Tech Map, from its records of 2026-10-08. https://trustbutveri.fyi/explorer/?mechanisms=M-0002,M-0012&implementations=M-0012:I-0006&chips=existing

Claims

Mechanisms2

Filters:× 23 of 25 match

Applied filters: Chips: Existing chips only. Not set (Any): Prover, Verifier devices on site, Prover cooperation, Minimum readiness, Attack testing, Keep hidden from the verifier.

Analysis

Applied filters: Chips: Existing chips only. Not set (Any): Prover, Verifier devices on site, Prover cooperation, Minimum readiness, Attack testing, Keep hidden from the verifier.

MechanismReadinessOpen flaws
Deterministic and bit-exact inference R31 significant1 minor
Model identity attestationTinfoil model identity (Modelwrap) R31 critical2 significantFamily context below
  • Open flaws: n critical n significant n minor
Claim coverageNo claims yet

Add claims to see which ones the mechanisms address.

Properties2 in production · 1 built for an adversarial prover
In production
Built for an adversarial prover
Deterministic and bit-exact inference
Attack testing2 mechanisms with published testing

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

Limits1 mechanism with open critical findings · 1 family with findings to check · 2 mechanisms with open significant findings
Open critical flaws
  • Inherits attacks on the underlying TEEs in Tinfoil model identity (Modelwrap)

    Critical when model identity must hold against an operator with physical access to an affected host. Tinfoil documents physical attacks as an enclave limitation. These are hardware-class demonstrations, not a published break of Modelwrap or Tinfoil's deployed verification chain.

    Tinfoil's model commitment and boot-time GPU check depend on the CPU attestation. The TEE findings distinguish Intel TDX forgery on DDR5, AMD SEV-SNP forgery on DDR4 in Battering RAM, and software-only RMPocalypse on platforms lacking AMD's fixes. TEE.fail recovered a guest OpenSSL key on AMD, not an AMD attestation key. Its GPU relay demonstration used an H100 with forged TDX evidence; it does not establish the same result for Tinfoil's H200 or B200 configurations. 13 14 17 18 19 20

    Response: Tinfoil acknowledges the physical-access boundary. The TEE.fail authors report that Intel and AMD treat interposer attacks as outside their threat models and recommend physically secure servers. AMD reports firmware fixes for RMPocalypse.

    Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

Family findings
  • Model identity attestation

    Context for Tinfoil model identity (Modelwrap). These findings concern the family or other implementations; applicability must be checked against their stated scope.

    • Underlying attestation can be forged or relayed in Model identity attestation

      Critical for the enclave route against an operator with physical access to affected hardware, or control of an unpatched SEV-SNP hypervisor. It does not apply to the recomputation route. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary.

      The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. 13 17 18 19 20 21

      Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

      Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

      Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this flaw is mitigated. Add

    • Launch-state attestation does not by itself cover weights loaded later in Model identity attestation

      Attestation measures launch state, and weights are read from disk after boot. A signature checked at load time does not stop a malicious hypervisor from altering the disk afterwards. Tinfoil reports mitigating this with dm-verity checks on every read. Unmeasured runtime configuration remains a general risk. 12 22

      Theoretical argument · Significant · Mitigated. On the record

    • For private models, a user can confirm consistency but not content in Model identity attestation

      When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy. 12 23

      Open question · Significant · Open. On the record

    • Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel in Model identity attestation

      The recomputation variant assumes that every input, output and seed is logged correctly, and that the attacker can neither predict nor manipulate which messages are sampled for verification. Legitimate nondeterminism concentrates at a few token positions, and slow leaks within the tolerated slack remain possible. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token, reducing the exfiltration slowdown from 146–254 times under benign prompts to 60–118 times. The attack targets the exfiltration bound, not the check that outputs match the declared model. 24 25

      Demonstrated attack · Significant · Open. On the record

      Related mechanism R1 Network taps and certifiers: Taps are proposed to copy and hash traffic on the monitored links, reducing reliance on the prover's own log. This still depends on the monitored boundary and trusted capture. A pointer, not evidence that this flaw is mitigated. Add

      Related mechanism R3 Deterministic and bit-exact inference: Bit-exact inference would remove the numerical tolerance that leaves this channel. A pointer, not evidence that this flaw is mitigated. In the proposal.

Open significant flaws
3 flaws in 2 mechanisms
  • Cross-hardware replay relies on reverse-engineered, closed behaviour in Deterministic and bit-exact inference

    Emulating one GPU's rounding on another requires reverse-engineering tensor-core arithmetic and modelling proprietary kernel choices. Hawkeye covers a subset of NVIDIA architectures and states that attention and other higher-level operations need further reverse engineering. For the bit-exact emulator, a proprietary Hopper kernel family is an open edge case. 1 3

    Open question · Significant · Open. On the record

  • Side channels, I/O leakage and denial of service are outside enclave protection in Tinfoil model identity (Modelwrap)

    Tinfoil's documentation lists timing, power and electromagnetic side channels, host observation of access patterns and I/O, denial of service, supply-chain compromise and rollback as limitations. 13

    Theoretical argument · Significant · Open. On the record

  • Private models can be checked only for consistency in Tinfoil model identity (Modelwrap)

    For unpublished weights, the root hash appears in the attestation without the weights being exposed. Users can then confirm only that they get the same model each time. 12

    Open question · Significant · Open. On the record

Open minor flaws
1 mechanism with minor findings
  • Some kernels remain genuinely nondeterministic in Deterministic and bit-exact inference

    The bit-exact work separates kernels that are deterministic but not batch-invariant from truly nondeterministic ones that use atomic functions. Some integer de-quantization kernels use atomic additions and remain nondeterministic, so exact replay needs backends that avoid them. 1

    Open question · Minor · Open. On the record

Possible additions1 for dependencies

Mechanisms on the map that are not in the proposal. Pointers, not recommendations.

Dependencies1 missing prerequisite · 6 blockers
Missing prerequisites
Blockers
6 blockers recorded
  • Deterministic and bit-exact inference
    • Batch-invariant kernels cost throughput: in Thinking Machines' Qwen3-8B test, an improved deterministic build took 42 s against 26 s for vLLM's default, and SGLang reports an average 34.35% slowdown on its FlashInfer and FlashAttention 3 backends. Performance & compatibility 2 4
    • Coverage is incomplete: the bit-exact emulator targets dense blocks on NVIDIA GPUs and excludes mixture-of-experts inference and training, and vLLM's batch-invariant mode is in beta, with open work on AMD hardware and speculative decoding. Performance & compatibility 1 5 26
    • Amodo's status page for the AI 2040 verification plan rates a reproducible inference stack for that plan as 'not started'. Performance & compatibility 27
    • Exact replay requires the prover to disclose weights, software versions, parallelism and batch sizes to whoever recomputes. Privacy & leakage 1 11
  • Model identity attestation
    • The underlying TEE attestation does not resist attackers with physical access to the host. Hardware trust. Waits on TEE remote attestation for AI workloads 13 17
    • No independent evaluation of the model-identity chain has been published. Adversarial validation
What the verifier sees1 unspecified · 2 depend on design

From the family or selected implementation's record.

Model weights

Depends on the design for Deterministic and bit-exact inference and Model identity attestation.

Inputs and outputs

Depends on the design for Deterministic and bit-exact inference.

Unspecified for Model identity attestation. Check the implementation record.

Exposure notes
Implementations6 systems
Deterministic and bit-exact inference
Model identity attestation
Sources27 cited
  1. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
  2. Defeating Nondeterminism in LLM Inference, H. He & Thinking Machines Lab (2025). Original
  3. Hawkeye: Reproducing GPU-Level Non-Determinism, E. Badash et al. (2026). Original
  4. Towards Deterministic Inference in SGLang and Reproducible RL Training, The SGLang Team (2025). Original
  5. Batch Invariance (vLLM documentation), vLLM project (2026). Original
  6. gensyn-ai/ree: Gensyn Reproducible Execution Environment (GitHub repository), Gensyn (2026). Original
  7. EigenCloud Brings Verifiable AI to Mass Market with EigenAI and EigenCompute Launches, EigenCloud (2025). Original
  8. Building Delphi: Pricing, Settlement, and Agentic Trading, D. Jedamski (2026). Original
  9. Reproducible Execution Environment (REE) (Gensyn documentation), Gensyn (2026). Original
  10. What is Delphi? (Delphi documentation), Gensyn (2026). Original
  11. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
  12. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
  13. A primer on secure enclaves, Tinfoil (2026). Original
  14. Backend infrastructure, Tinfoil (2026). Original
  15. How verification works in Tinfoil, Tinfoil (2026). Original
  16. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). Original
  17. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
  18. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
  19. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
  20. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
  21. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
  22. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
  23. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original
  24. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
  25. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
  26. [Feature]: Batch Invariant Feature and Performance Optimization (vLLM issue #27433), vLLM project contributors (2025). Original
  27. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original

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Filter mechanisms

Filters apply to mechanisms only. They describe the setting a proposal is for, and all are off by default. A mechanism that a filter rules out is flagged and does not count towards claim coverage. Selected implementations use their own record fields. A match means not excluded; conditional or unspecified exposure stays with a note. Passing a filter does not establish that the assumptions hold in a deployment.

23 of 25 mechanisms match · Clear all

Prover

How far can the party being checked be trusted?

The prover is the party being checked. Semi-trusted designs rely on part of its stack: usually the chip vendor's hardware root of trust, its firmware or counters, or its supply-chain records. Adversarial designs aim to hold even if it cheats wherever the checks allow, within their stated assumptions.

Keeps mechanisms whose threat model holds against at least this prover. Adversarial is the strongest assumption. Definitions

Verifier devices on site

May the verifier install its own hardware at the prover's sites?

Some mechanisms need a device the verifier owns or trusts at the prover's facility, such as a network tap, a bandwidth limiter or a sealed sensor. Choose Not allowed when the setting rules that out. Inspectors are not covered.

"Not allowed" removes mechanisms that need a retrofit device, such as a network tap or a sealed sensor. Definitions

Prover cooperation

How much must the prover take part?

Required: the prover takes part, for example by logging requests, producing proofs or opening records. Partial: some access, such as installing a device. Not required: works from outside, such as satellite imagery.

"Partial at most" removes mechanisms that need the prover's active participation. "Not required" keeps only those that work without it. Definitions

Chips

May the proposal depend on new chip designs?

New chip features take years to reach a deployed fleet and cover only chips made after they ship. Mechanisms that use shipping features, such as trusted execution environments or performance counters, stay.

"Existing chips only" removes mechanisms that need changes to future chip designs. Definitions

Minimum readiness

How mature must each mechanism be?

A level describes the public evidence for a mechanism's stated use, not its cost or feasibility. R3 can still have open critical flaws.

Keeps mechanisms whose readiness level is at least this one. Definitions

Attack testing

How hard has each mechanism been attacked in public?

The strongest published attempt to break the mechanism for its verification use: a security analysis, red-teaming by its developers or collaborators, or a red team independent of them.

Keeps mechanisms whose strongest published attack testing is at least this. Definitions

Keep hidden from the verifier

What must the verifier never see? Choose any.

Model weights: the checked model's parameters. Inputs and outputs: the requests a deployed model serves and its responses. Training data: what a model was trained on. Each mechanism's exposure is the editors' reading of its record: shown, depends on the design (kept, with a note), hidden, not involved, or unspecified for a selected implementation. Code and configuration are not covered yet.

Removes mechanisms that show the asset to the verifier. Conditional or unspecified exposure stays with a note and needs checking against the privacy requirement.

Claims

A claim is something one party wants to verify about another party's AI hardware or software. Each claim's number shows how the proposal addresses it.

  • Addressed. A mechanism in the proposal is aimed at this claim and is not excluded by the filters.
  • Partly addressed. Only supporting mechanisms, or mechanisms aimed at it that the filters exclude.
  • Unaddressed. No mechanism in the proposal addresses this claim.

Addressed means a mechanism in the proposal is aimed at the claim and is not excluded by your filters. It does not mean the claim is verified: check its assessed use, readiness, assumptions and open flaws.

All claims

Mechanisms

A mechanism is a general technique for verifying claims. Its badge is its readiness level for its stated use. An optional implementation choice narrows its assumptions, assessed use and claim links to that record. Lines join it to the claims it addresses. Click a line for details.Under its name it lists the claims it is aimed at or supports.

  • Aimed at the claim: verifying it is a direct purpose of the mechanism.
  • Supports the claim: helps verify it without being aimed at it.
  • Faint: excluded by your filters, so it does not count towards claim coverage.

All mechanisms

Overview

One row per mechanism in the proposal. Every mark comes from that mechanism's record, as listed in the panels below; what the verifier sees is the editors' reading of the record's text. Flaw counts are per mechanism. Summary counts name mechanisms with open findings, not a sum of attacks. Choosing an implementation narrows each row to that record's assessed use; family findings remain as context.

What the verifier sees

For model weights, inputs and outputs, and training data. This is the editors' reading of each mechanism's record (its threat model, how it works and its limitations), not a field of the record. Shown: the verifier sees it. Depends: on the design or variant, or the verifier sees only samples. Hidden: the verifier sees only commitments, hashes, proofs or results. Not involved: the record does not handle it. Unspecified: the selected implementation has no asset-specific assessment here.

Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open flaw or a dependency. They are pointers, not recommendations: each brings its own readiness level and flaws, and none is claimed to close a flaw. Links from flaws are the editors' reading of the two records.

Start from a published design

Choosing a design loads the mechanisms its record realises or depends on. If the proposal has no claims yet, it also loads the claims that record says the design addresses.

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