Proposal Explorer

Add claims to see which ones the mechanisms address.

Operational use

• Operational use Hardware-attested weight binding for showing clients that the served weights match a committed hash

No new hardware needed

On-chip telemetry from timing, memory and performance counters and Hardware-attested weight binding

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• On-chip telemetry from timing, memory and performance counters: Red-teamed
• Hardware-attested weight binding, Tinfoil model identity (Modelwrap): Analysis

Open critical failures

• Inherits attacks on the underlying TEEs in Tinfoil model identity (Modelwrap)

  Critical when model identity must hold against an operator with physical access to an affected host. Tinfoil documents physical attacks as an enclave limitation. These are hardware-class demonstrations, not a published break of Modelwrap or Tinfoil's deployed verification chain.

  Tinfoil's model commitment and boot-time GPU check depend on the CPU attestation. The TEE findings distinguish Intel TDX forgery on DDR5, AMD SEV-SNP forgery on DDR4 in Battering RAM, and software-only RMPocalypse on platforms lacking AMD's fixes. TEE.fail recovered a guest OpenSSL key on AMD, not an AMD attestation key. Its GPU relay demonstration used an H100 with forged TDX evidence; it does not establish the same result for Tinfoil's H200 or B200 configurations. ^{7 8 11 12 13 14}

  Response: Tinfoil acknowledges the physical-access boundary. The TEE.fail authors report that Intel and AMD treat interposer attacks as outside their threat models and recommend physically secure servers. AMD reports firmware fixes for RMPocalypse.

  Known failure · Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

Family findings

• Hardware-attested weight binding

  Context for Tinfoil model identity (Modelwrap). Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there.

  • Underlying attestation can be forged or relayed in Hardware-attested weight binding

    Critical for weight binding against an operator with physical access to affected hardware, or with control of the hypervisor on an AMD SEV-SNP platform without AMD's fixes. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary.

    The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. ^{7 11 12 13 14 15}

    Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

    Known failure · Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

    Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this failure is mitigated. Add

  • Launch-state attestation does not by itself cover weights loaded later in Hardware-attested weight binding

    Attestation measures launch state, and weights are read from disk after boot. A signature checked at load time does not stop a malicious hypervisor from altering the disk afterwards. Tinfoil reports mitigating this with dm-verity checks on every read. Unmeasured runtime configuration remains a general risk. ^{4 6}

    Known failure · Theoretical argument · Significant · Mitigated. On the record

  • For private models, a user can confirm consistency but not content in Hardware-attested weight binding

    When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy. ^{6 16}

    Scope limitation · Open question. On the record

Open significant failures

2 failures in 1 mechanism

• Adversarially disguised fine-tuning partly evades classification in On-chip telemetry from timing, memory and performance counters

  Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware. ³

  Known failure · Demonstrated attack · Significant · Open. On the record

• Counters leak information about protected workloads in On-chip telemetry from timing, memory and performance counters

  Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality. ^{4 5}

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Software-read telemetry can be forged by the operator in On-chip telemetry from timing, memory and performance counters

  NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized. ^{1 3}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing. A pointer, not evidence that this failure is mitigated. Add

• Timing challenges do not identify the individual chip in On-chip telemetry from timing, memory and performance counters

  GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use. ¹

  Scope limitation · Theoretical argument. On the record

• Side channels, I/O leakage and denial of service are outside enclave protection in Tinfoil model identity (Modelwrap)

  Tinfoil's documentation lists timing, power and electromagnetic side channels, host observation of access patterns and I/O, denial of service, supply-chain compromise and rollback as limitations. ⁷

  Scope limitation · Theoretical argument. On the record

• Private models can be checked only for consistency in Tinfoil model identity (Modelwrap)

  For unpublished weights, the root hash appears in the attestation without the weights being exposed. Users can then confirm only that they get the same model each time. ⁶

  Scope limitation · Open question. On the record

Open questions

• No quantified error rates or formal thresholds for timing primitives in On-chip telemetry from timing, memory and performance counters

  Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work. ¹

  Open question · Open question. On the record

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Operational use TEE remote attestation for AI workloads Add
  • Hardware-attested weight binding waits on it. The underlying TEE attestation does not resist attackers with physical access to the host.
  • On-chip telemetry from timing, memory and performance counters depends on it.
• Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors Add

  Excluded by filters: needs new chips

  • On-chip telemetry from timing, memory and performance counters waits on it. Shipping accelerators need a tamper-resistant, authenticated telemetry path.

Missing prerequisites

• Operational use TEE remote attestation for AI workloads needed by On-chip telemetry from timing, memory and performance counters and Hardware-attested weight binding Add

Shared foundations

• TEE remote attestation for AI workloads relied on by On-chip telemetry from timing, memory and performance counters and Hardware-attested weight binding

Blockers

6 blockers recorded

• On-chip telemetry from timing, memory and performance counters
  • Shipping accelerators need a tamper-resistant, authenticated telemetry path. Hardware trust. Waits on Hardware-enabled guarantees (flexHEG) and guarantee processors ^{2 3}
  • NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. Privacy & leakage ^{4 5}
  • Continuous challenge puzzles cost power and throughput on production workloads. Performance & compatibility ¹
  • Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. Adversarial validation ³
• Hardware-attested weight binding
  • The underlying TEE attestation does not resist attackers with physical access to the host. Hardware trust. Waits on TEE remote attestation for AI workloads ^{7 11}
  • No independent evaluation of the model-identity chain has been published. Adversarial validation

From the family or selected implementation's record. ?

Model weights

Depends on the design for On-chip telemetry from timing, memory and performance counters and Hardware-attested weight binding.

Inputs and outputs

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Unspecified for Hardware-attested weight binding. Check the implementation record.

Training data

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Hardware-attested weight binding.

On-chip telemetry from timing, memory and performance counters

None on the map

Hardware-attested weight binding

• Research demo Attestable Audits Research prototype, University of Cambridge
• Research demo PAL*M Research prototype, University of Waterloo
• Operational use Tinfoil model identity (Modelwrap) Product, Tinfoil

1. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
2. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). Original
3. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). Original
4. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
5. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original
6. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
7. A primer on secure enclaves, Tinfoil (2026). Original
8. Backend infrastructure, Tinfoil (2026). Original
9. How verification works in Tinfoil, Tinfoil (2026). Original
10. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). Original
11. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
12. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
13. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
14. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
15. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
16. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original