Proposal Explorer

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Timed challenge-response and memory-occupation challenges

No new hardware needed

Chip registries and manufacturing records

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Timed challenge-response and memory-occupation challenges, Data-centre memory challenging: Analysis
• Chip registries and manufacturing records: Analysis

Family findings

• Timed challenge-response and memory-occupation challenges

  Context for Data-centre memory challenging. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there.

  • Timing-based software attestation has been broken in practice in Timed challenge-response and memory-occupation challenges

    Castelluccia et al. implemented two generic attacks, one based on a return-oriented rootkit and one on code compression, together with specific attacks on SWATT and ICE-based schemes, on commodity sensor nodes. They conclude that secure time-based attestation is "very difficult, if not impossible, to design correctly". The attacks target embedded schemes, not AI accelerators. ^{2 3}

    Response: Perrig and van Doorn, two of the designers of SWATT and ICE, replied in August 2010. They argue that the rootkit attack defeats a naive implementation, not a property the schemes claim, and that the SWATT attack was run on a re-implementation on a chip with eight times the program memory, where SWATT's own chip is almost always full of code. They accept that the attack on ICE works.

    Known failure · Demonstrated attack · Significant · Disputed. On the record

  • Remote memory narrows the timing margin in Timed challenge-response and memory-occupation challenges

    Data-centre remote memory access returns in about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview says verification of memory saturation depends on ruling out remote access by latency or physical disconnection. It names pre-staging data into local memory as the remaining evasion and proposes an unpredictable, capacity-filling challenge to close it. ¹

    Known failure · Theoretical argument · Significant · Open. On the record

    Related mechanism Research demo Bandwidth limits and compartmentalization: Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced. A pointer, not evidence that this failure is mitigated. Add

  • Error rates not quantified in Timed challenge-response and memory-occupation challenges

    Monfared et al. show separable timing distributions. Their acceptance rule passes a GPU when its mean time per round stays at or below a chosen maximum, and an appendix outlines statistical tests for the proof-of-work puzzle. They leave hardware-specific threshold values to future work and report no false-positive or false-negative rates. ⁴

    Open question · Open question. On the record

Open significant failures

2 failures in 2 mechanisms

• Remote memory narrows the timing margin in Data-centre memory challenging

  A remote memory access round trip takes about 1–2 µs over InfiniBand or RoCE, against about 70–200 ns for a local DRAM read. The overview says verification of memory saturation depends on ruling out remote access, by response latency or by physical disconnection. ¹

  Known failure · Theoretical argument · Significant · Open. On the record

• Documents and serial numbers can be forged in Chip registries and manufacturing records

  Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. ⁶

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Presence does not show absence in Data-centre memory challenging

  A check that data is present does not show that nothing else is stored. The overview names pre-staging data into local memory before a challenge as the remaining evasion, and proposes an unpredictable, capacity-filling challenge to close it. ¹

  Scope limitation · Theoretical argument. On the record

• Records cover only chips that were recorded in Chip registries and manufacturing records

  A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. ^{7 9}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this failure is mitigated. Add

• Insiders could alter records before they are fixed in Chip registries and manufacturing records

  Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. ⁷

  Scope limitation · Theoretical argument. On the record

Not yet demonstrated

Proposed Timed challenge-response and memory-occupation challenges and Proposed Chip registries and manufacturing records

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Research demo Bandwidth limits and compartmentalization Add
  • Timed challenge-response and memory-occupation challenges waits on it. Remote memory access must be excluded during challenges.

Missing prerequisites

• Research demo Bandwidth limits and compartmentalization needed by Timed challenge-response and memory-occupation challenges Add

Blockers

7 blockers recorded

• Timed challenge-response and memory-occupation challenges
  • No network-level probe has been shown to distinguish one server's memory contents from another's. Adversarial validation ¹
  • Most of the design needs a probe in close proximity to the challenged memory. Access & governance ¹
  • Filling a pod's volatile memory takes tens of minutes, and on-board SSDs take hours. Performance & compatibility ¹
  • Remote memory access must be excluded during challenges. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization ¹
• Chip registries and manufacturing records
  • No implementation of an AI chip registry has been publicly reported, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance ^{5 6}
  • Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust ^{5 6 7}
  • Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute ^{7 9}

From the family or selected implementation's record. ?

Model weights

Not involved: Chip registries and manufacturing records.

Unspecified for Timed challenge-response and memory-occupation challenges. Check the implementation record.

Inputs and outputs

Not involved: Chip registries and manufacturing records.

Unspecified for Timed challenge-response and memory-occupation challenges. Check the implementation record.

Training data

Not involved: Chip registries and manufacturing records.

Unspecified for Timed challenge-response and memory-occupation challenges. Check the implementation record.

Timed challenge-response and memory-occupation challenges

• Proposed Data-centre memory challenging Proposed architecture, Machine Intelligence Research Institute
• Research demo GPU contention probes Research prototype
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Research demo SAGE Research prototype
• Research demo VRAM-residency challenge Research prototype

Chip registries and manufacturing records

None on the map

1. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
2. On the Difficulty of Software-Based Attestation of Embedded Devices, C. Castelluccia et al. (2009). Original
3. Refutation of "On the Difficulty of Software-Based Attestation of Embedded Devices", A. Perrig & L. van Doorn (2010). Original
4. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
5. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
6. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
7. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
8. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
9. Covert AI Projects, B. Halstead & T. Larsen (2026). Original