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A verification proposal from the AI Verification Tech Map, from its records of 2026-10-09. https://trustbutveri.fyi/explorer/?mechanisms=M-0023,M-0020,M-0012&chips=existing&tested=analysis

Claims

Mechanisms3

Filters:×× 22 of 25 match · Clear

Applied filters: Chips: Existing chips only; Attack testing: Published analysis. Not set (Any): Prover, Verifier devices on site, Prover cooperation, Minimum development status, Keep hidden from the verifier.

Analysis

Applied filters: Chips: Existing chips only; Attack testing: Published analysis. Not set (Any): Prover, Verifier devices on site, Prover cooperation, Minimum development status, Keep hidden from the verifier.

  • Open failures: n critical n significant n minor
Claim coverageNo claims yet

Add claims to see which ones the mechanisms address.

Properties1 with operational use · 1 built for an adversarial prover
Operational use
Built for an adversarial prover
Remote detection of data centres
Failures since mitigated
  • Launch-state attestation does not by itself cover weights loaded later in Hardware-attested weight binding 9 19
Attack testing3 mechanisms with published testing

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

Limits1 mechanism with open critical failures · 6 scope limitations · 1 open question · 1 not yet demonstrated · 1 mechanism with open significant failures
Open critical failures
  • Underlying attestation can be forged or relayed in Hardware-attested weight binding

    Critical for weight binding against an operator with physical access to affected hardware, or with control of the hypervisor on an AMD SEV-SNP platform without AMD's fixes. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary.

    The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. 4 7 10 11 12 20

    Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

    Known failure · Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

    Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this failure is mitigated. Add

Open significant failures
2 failures in 1 mechanism
  • Components outside the attested boundary in Safeguard attestation

    In the proof-of-guardrail experiments, the guardrail model and the agent's backend model were both reached through external APIs, and the authors leave the decision to trust those APIs to the verifier. The measured wrapper must also have no vulnerability that lets the unmeasured agent bypass the guardrail, for example by executing arbitrary commands inside the enclave. The code's README states that the enclave does not currently restrict the agent's arbitrary command execution, which could be used to bypass guardrails. 1 2

    Known failure · Theoretical argument · Significant · Open. On the record

  • Memory-bus interposition extracts attestation keys and forges attestations in Safeguard attestation

    Applies to variants using the affected Intel or AMD trust roots. PAL*M excludes physical attacks. A TDX-backed safeguard claim against a physical host attacker would be defeated, but these studies do not demonstrate a break of the AWS Nitro proof-of-guardrail prototype or of verifier-side recomputation.

    The TEE findings cover DDR5 attacks on Intel TDX, the H100 relay demonstration, DDR4 attacks on AMD SEV-SNP, and software-only SEV-SNP forgery before AMD's fixes. These are inherited hardware limits; a governance analysis explains why physical access matters in a treaty setting. 1 4 7 8 9 10 11 12 13

    Response: Intel and AMD place the physical attack class outside their threat models, according to the researchers. AMD reports firmware fixes for RMPocalypse.

    Known failure · Demonstrated attack · Significant · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

    Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this failure is mitigated. Add

Scope limitations
  • Attestation shows a safeguard ran, not that it is effective in Safeguard attestation

    Proof of guardrail ensures that the guardrail executed, but the guardrail can still err or be jailbroken. Because the guardrail must be open source, a malicious developer can attack it with jailbreaks while still presenting a valid proof. In the authors' evaluation, Llama Guard 3 reached an F1 score of 0.56 on the unsafe class of the ToxicChat dataset. The authors state that proof of guardrail should not be interpreted or advertised as proof of safety. 1

    Scope limitation · Theoretical argument. On the record

  • Selective attestation leaves traffic uncovered in Safeguard attestation

    Attestations are issued per response. In the prototype, the agent offers them when it receives high-stakes questions, so nothing shows that unattested traffic went through the same path. PAL*M's authors note that a prover could cherry-pick favourable executions, and suggest verifier-published nonces or requesting only session-level proofs. A governance analysis notes that auditors also need assurance that all activity is accounted for, since a host could start a second confidential virtual machine that bypasses monitoring. 1 4 9

    Scope limitation · Theoretical argument. On the record

    Related mechanism Research demo On-chip telemetry from timing, memory and performance counters: On-chip counters are a proposed route to evidence about everything a chip runs, including a second virtual machine that skips the safeguard. A pointer, not evidence that this failure is mitigated. Add

  • Measurements may omit behaviour-relevant configuration or runtime changes in Safeguard attestation

    Every component that influences inference behaviour must be covered by the launch measurement, including feature flags, environment variables and invocation arguments. A launch measurement also does not show that a program keeps running as measured if the kernel is later compromised. 9

    Scope limitation · Theoretical argument. On the record

  • Facilities can be disguised or hidden in Remote detection of data centres

    Halstead and Larsen discuss two ways to hide a facility. One is to disguise it as a legitimate industrial site. The other is to build it underground, with cooling that avoids visible heat plumes. They note that the underground option requires bespoke engineering. 14

    Scope limitation · Theoretical argument. On the record

  • Small sites may not be detectable in Remote detection of data centres

    Halstead and Larsen conclude that a sufficiently small covert project could not be ruled out with confidence. In their estimates, the chance of detection is lower for smaller sites. Krawec notes that small data centres in existing buildings may lack the distinctive features of large facilities. 14 16

    Scope limitation · Theoretical argument. On the record

    Related mechanism Proposed Chip registries and manufacturing records: Accounts for chips from the fab onwards, which does not depend on a site being visible. A pointer, not evidence that this failure is mitigated. Add

  • For private models, a user can confirm consistency but not content in Hardware-attested weight binding

    When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy. 19 24

    Scope limitation · Open question. On the record

Open questions
  • Search for unknown sites is undemonstrated in Remote detection of data centres

    Krawec reports that telling data centres apart from other industrial facilities systematically is difficult. Automating detection would need large amounts of training imagery and a purpose-trained model. In Krawec's words, automated data-centre detection "remains primarily conceptual at present". 16

    Open question · Open question. On the record

Possible additions1 for open failures · 1 for dependencies

Mechanisms on the map that are not in the proposal. Pointers, not recommendations.

    • Safeguard attestation waits on it. Frontier model inference typically needs several GPUs, GPU confidential computing is less mature than CPU support, and CPU inference, which an enclave prototype had to use, ran about 100 times slower than GPU inference.
    • Safeguard attestation waits on it. Trust rests on a small number of hardware vendors, and a per-CPU Intel attestation key has been extracted by physical attack.
    • Hardware-attested weight binding waits on it. Attestation that resists physical attackers, for the enclave variant.
  • Excluded by filters: needs new chips

    • Bears on the open critical failure “Underlying attestation can be forged or relayed” in Hardware-attested weight binding. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
    • Bears on the open significant failure “Memory-bus interposition extracts attestation keys and forges attestations” in Safeguard attestation. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
Dependencies1 missing prerequisite · 1 shared foundation · 9 blockers
Missing prerequisites
Shared foundations
Blockers
9 blockers recorded
  • Safeguard attestation
    • No published design shows that all of a provider's traffic passes through the attested safeguard path; current evidence covers individual attested responses. Coverage & hidden compute 1 9
    • Frontier model inference typically needs several GPUs, GPU confidential computing is less mature than CPU support, and CPU inference, which an enclave prototype had to use, ran about 100 times slower than GPU inference. Performance & compatibility. Waits on TEE remote attestation for AI workloads 9 24
    • Trust rests on a small number of hardware vendors, and a per-CPU Intel attestation key has been extracted by physical attack. Hardware trust. Waits on TEE remote attestation for AI workloads 7 9
    • Safeguard evidence must be bound to the model actually served, which depends on model-identity attestation. Evidence binding. Waits on Hardware-attested weight binding 19 24
    • No independent red-team or audit of a safeguard-attestation system has been published, and the available prototypes are described by their authors as proofs of concept that have not been stress-tested by a counterparty. Adversarial validation 2 6
  • Remote detection of data centres
    • Wide-area, automated detection of data centres is not yet practical and needs large training datasets. Coverage & hidden compute 16
    • No measured detection or false-alarm rates for finding undeclared facilities have been published. Adversarial validation 14 16
    • Recent high-resolution imagery is costly, is limited by weather and needs trained analysts. Access & governance 16
  • Hardware-attested weight binding
    • Attestation that resists physical attackers, for the enclave variant. Hardware trust. Waits on TEE remote attestation for AI workloads 7
What the verifier sees1 unspecified · 1 depend on design

From the family or selected implementation's record.

Model weights

Depends on the design for Safeguard attestation.

Hidden by Hardware-attested weight binding.

Not involved: Remote detection of data centres.

Inputs and outputs

Depends on the design for Safeguard attestation.

Not involved: Remote detection of data centres.

Unspecified for Hardware-attested weight binding. Check the implementation record.

Exposure notes
  • Safeguard attestation: The enclave route signs hashes of the safeguard, request and response; a low-trust design has the verifier re-run and screen sampled requests itself.
  • Remote detection of data centres: Works from outside the facility; it does not handle model data.
  • Hardware-attested weight binding: Verifiers check a hash commitment to the weights, carried in a hardware attestation, and need no access to the weights themselves. The mechanism does not specify whether prompts and outputs are disclosed to a verifier. It involves no training data. 4 19 24
Implementations3 systems
Safeguard attestation
None on the map
Remote detection of data centres
None on the map
Hardware-attested weight binding
Sources24 cited
  1. Proof-of-Guardrail in AI Agents and What (Not) to Trust from It, X. Jin et al. (2026). Original
  2. Verifiable-ClawGuard: proof-of-guardrail reference code, SaharaLabsAI (2026). Original
  3. Safety Without Compromising on Privacy, D. McCann-Sayles et al. (2026). Original
  4. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
  5. Enabling Verifiably-Scoped Monitoring through Large Language Models and Trusted Compute, B. Penchas et al. (2026). Original
  6. Auditor-in-a-Box: Tools for Third-Party Auditing, R. Rinberg & B. Penchas (2026). Original
  7. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
  8. DDRop: Active Memory Interposer Attacks on Confidential VMs by Dropping DDR5 Writes, J. De Meulemeester et al. (2026). Original
  9. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
  10. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
  11. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
  12. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
  13. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
  14. Covert AI Projects, B. Halstead & T. Larsen (2026). Original
  15. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
  16. Tracking Hyperscale AI Data Center Growth with Satellite Imagery, C. Krawec (2026). Original
  17. Introducing the Frontier Data Centers Hub, Epoch AI (2025). Original
  18. AI Data Centers Documentation – Methodology, Epoch AI (2026). Original
  19. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
  20. A primer on secure enclaves, Tinfoil (2026). Original
  21. Backend infrastructure, Tinfoil (2026). Original
  22. How verification works in Tinfoil, Tinfoil (2026). Original
  23. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). Original
  24. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original

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Filter mechanisms

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22 of 25 mechanisms match · Clear all

Prover

How far can the party being checked be trusted?

The prover is the party being checked. Semi-trusted designs rely on part of its stack: usually the chip vendor's hardware root of trust, its firmware or counters, or its supply-chain records. Adversarial designs aim to hold even if it cheats wherever the checks allow, within their stated assumptions.

Keeps mechanisms whose threat model holds against at least this prover. Adversarial is the strongest assumption. Definitions

Verifier devices on site

May the verifier install its own hardware at the prover's sites?

Some mechanisms need a device the verifier owns or trusts at the prover's facility, such as a network tap, a bandwidth limiter or a sealed sensor. Choose Not allowed when the setting rules that out. Inspectors are not covered.

"Not allowed" removes mechanisms that need a retrofit device, such as a network tap or a sealed sensor. Definitions

Prover cooperation

How much must the prover take part?

Required: the prover takes part, for example by logging requests, producing proofs or opening records. Partial: some access, such as installing a device. Not required: works from outside, such as satellite imagery.

"Partial at most" removes mechanisms that need the prover's active participation. "Not required" keeps only those that work without it. Definitions

Chips

May the proposal depend on new chip designs?

New chip features take years to reach a deployed fleet and cover only chips made after they ship. Mechanisms that use shipping features, such as trusted execution environments or performance counters, stay.

"Existing chips only" removes mechanisms that need changes to future chip designs. Definitions

Minimum development status

Development status

A level describes the public evidence for a mechanism's stated use, not its cost or feasibility. R3 can still have open critical flaws.

Keeps mechanisms whose readiness level is at least this one. Definitions

Attack testing

How hard has each mechanism been attacked in public?

The strongest published attempt to break the mechanism for its verification use: a security analysis, red-teaming by its developers or collaborators, or a red team independent of them.

Keeps mechanisms whose strongest published attack testing is at least this. Definitions

Keep hidden from the verifier

What must the verifier never see? Choose any.

Model weights: the checked model's parameters. Inputs and outputs: the requests a deployed model serves and its responses. Training data: what a model was trained on. Each mechanism's exposure is the editors' reading of its record: shown, depends on the design (kept, with a note), hidden, not involved, or unspecified for a selected implementation. Code and configuration are not covered yet.

Removes mechanisms that show the asset to the verifier. Conditional or unspecified exposure stays with a note and needs checking against the privacy requirement.

Claims

A claim is something one party wants to verify about another party's AI hardware or software. Each claim's number shows how the proposal addresses it.

  • Addressed. A mechanism in the proposal is aimed at this claim and is not excluded by the filters.
  • Partly addressed. Only supporting mechanisms, or mechanisms aimed at it that the filters exclude.
  • Unaddressed. No mechanism in the proposal addresses this claim.

Addressed means a mechanism in the proposal is aimed at the claim and is not excluded by your filters. It does not mean the claim is verified: check its assessed use, development status, security evidence, assumptions and findings.

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Mechanisms

A mechanism is a general technique for verifying claims. Its badge is its development status for its stated use. An optional implementation choice narrows its assumptions, assessed use and claim links to that record. Lines join it to the claims it addresses. Click a line for details.Under its name it lists the claims it is aimed at or supports.

  • Aimed at the claim: verifying it is a direct purpose of the mechanism.
  • Supports the claim: helps verify it without being aimed at it.
  • Faint: excluded by your filters, so it does not count towards claim coverage.

All mechanisms

Overview

One row per mechanism in the proposal. Every mark comes from that mechanism's record, as listed in the panels below; what the verifier sees is the editors' reading of the record's text. Failure counts are per mechanism. Summary counts name mechanisms with open failures, not a sum of attacks. Choosing an implementation narrows each row to that record's assessed use; family findings remain as context. Findings are grouped as known failures, scope limitations and open questions. Only known failures count as failures. Counts are an inventory of published findings, not a risk score.

What the verifier sees

For model weights, inputs and outputs, and training data. This is the editors' reading of each mechanism's record (its threat model, how it works and its limitations), not a field of the record. Shown: the verifier sees it. Depends: on the design or variant, or the verifier sees only samples. Hidden: the verifier sees only commitments, hashes, proofs or results. Not involved: the record does not handle it. Unspecified: the selected implementation has no asset-specific assessment here.

Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open failure or a dependency. They are pointers, not recommendations: each brings its own readiness level and findings, and none is claimed to close a failure. Links from failures are the editors' reading of the two records.

Start from a published design

Choosing a design loads the mechanisms its record realises or depends on. If the proposal has no claims yet, it also loads the claims that record says the design addresses.

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