Proposal Explorer

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Memory wiping and proofs of secure erasure and Timed challenge-response and memory-occupation challenges

No new hardware needed

Memory wiping and proofs of secure erasure and Timed challenge-response and memory-occupation challenges

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Memory wiping and proofs of secure erasure: Analysis
• Timed challenge-response and memory-occupation challenges: Analysis

Open significant failures

2 failures in 2 mechanisms

• Outside help during challenges in Memory wiping and proofs of secure erasure

  Classic proofs of secure erasure assume the device is isolated during the protocol. Bursuc et al. relax this to a bound on how close a helper can be, enforced by round-trip times. In data centres, remote memory access has round trips of about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview therefore says verification depends on ruling out RDMA by latency or physical disconnection. ^{3 4}

  Known failure · Theoretical argument · Significant · Open. On the record

  Related mechanism Research demo Timed challenge-response and memory-occupation challenges: Timed challenges bound how far away a helper can be by how quickly it must answer. A pointer, not evidence that this failure is mitigated. In the proposal.

  Related mechanism Research demo Bandwidth limits and compartmentalization: Removing or capping links between groups of accelerators limits remote memory access during a challenge. A pointer, not evidence that this failure is mitigated. Add

• Remote memory narrows the timing margin in Timed challenge-response and memory-occupation challenges

  Data-centre remote memory access returns in about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview says verification of memory saturation depends on ruling out remote access by latency or physical disconnection. It names pre-staging data into local memory as the remaining evasion and proposes an unpredictable, capacity-filling challenge to close it. ⁴

  Known failure · Theoretical argument · Significant · Open. On the record

  Related mechanism Research demo Bandwidth limits and compartmentalization: Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced. A pointer, not evidence that this failure is mitigated. Add

Scope limitations

• Memory the wipe cannot reach in Memory wiping and proofs of secure erasure

  Amodo's inventory of a GB200 system lists many memory stores beyond GPU HBM and host DRAM. It notes that SSD controller DRAM sits on a private bus that host commands cannot read or write, and that its optimized algorithm leaves 25 GiB of HBM unattested. It also asks how switch memory could be wiped. ^{5 6}

  Scope limitation · Open question. On the record

• Gap between erased and total memory in Memory wiping and proofs of secure erasure

  Bursuc et al. note that memory left between the erased region and the device's full memory could hold data, and that their bounds are tighter only against a restricted adversary. ³

  Scope limitation · Theoretical argument. On the record

Open questions

• Error rates not quantified in Timed challenge-response and memory-occupation challenges

  Monfared et al. show separable timing distributions. Their acceptance rule passes a GPU when its mean time per round stays at or below a chosen maximum, and an appendix outlines statistical tests for the proof-of-work puzzle. They leave hardware-specific threshold values to future work and report no false-positive or false-negative rates. ⁹

  Open question · Open question. On the record

Not yet demonstrated

Proposed Memory wiping and proofs of secure erasure

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Research demo Bandwidth limits and compartmentalization Add
  • Bears on the open significant failure “Outside help during challenges” in Memory wiping and proofs of secure erasure. Removing or capping links between groups of accelerators limits remote memory access during a challenge.
  • Bears on the open significant failure “Remote memory narrows the timing margin” in Timed challenge-response and memory-occupation challenges. Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced.
  • Timed challenge-response and memory-occupation challenges waits on it. Outside help, such as remote memory, must be excluded during challenges.

Blockers

6 blockers recorded

• Memory wiping and proofs of secure erasure
  • Wipes take time: tens of minutes for a pod's volatile memory and hours for SSDs, displacing work. Performance & compatibility ^{4 5 6}
  • Timed challenges must exclude remote memory and other helpers. Coverage & hidden compute. Waits on Timed challenge-response and memory-occupation challenges ^{3 4}
  • All memory stores in a system must be inventoried and wiped at the same time. Coverage & hidden compute ⁵
• Timed challenge-response and memory-occupation challenges
  • No network-level memory challenge across data-centre servers has been demonstrated. Adversarial validation ⁴
  • Challenges that fill memory displace workloads; filling a pod's volatile memory takes tens of minutes and SSDs take hours. Performance & compatibility ^{4 9}
  • Outside help, such as remote memory, must be excluded during challenges. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization ⁴

From the family or selected implementation's record. ?

Model weights

Not involved: Memory wiping and proofs of secure erasure and Timed challenge-response and memory-occupation challenges.

Inputs and outputs

Not involved: Memory wiping and proofs of secure erasure and Timed challenge-response and memory-occupation challenges.

Training data

Not involved: Memory wiping and proofs of secure erasure and Timed challenge-response and memory-occupation challenges.

Memory wiping and proofs of secure erasure

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute

Timed challenge-response and memory-occupation challenges

• Proposed Data-centre memory challenging Proposed architecture, Machine Intelligence Research Institute
• Research demo GPU contention probes Research prototype
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Research demo SAGE Research prototype
• Research demo VRAM-residency challenge Research prototype

1. Verification Plan, R. Dean (2026). Original
2. Secure Code Update for Embedded Devices via Proofs of Secure Erasure, D. Perito & G. Tsudik (2010). Original
3. Software-Based Memory Erasure with Relaxed Isolation Requirements, S. Bursuc et al. (2024). Original
4. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
5. Memory Wipes - Performance Analysis, Amodo Design (2026). Original
6. Improving Disk Wiping Speed for Memory Wipes, Amodo Design (2026). Original
7. Amodo-Design/PoSE-Memory-Wiping (GitHub repository), Amodo Design (2026). Original
8. Empirical Evaluation of Memory-Erasure Protocols, R. Gil-Pons et al. (2025). Original
9. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
10. SAGE: Software-based Attestation for GPU Execution, A. Ivanov et al. (2023). Original
11. SWATT: SoftWare-based ATTestation for Embedded Devices, A. Seshadri et al. (2004). Original
12. Proofs of Space, S. Dziembowski et al. (2015). Original
13. On the Difficulty of Software-Based Attestation of Embedded Devices, C. Castelluccia et al. (2009). Original
14. Refutation of "On the Difficulty of Software-Based Attestation of Embedded Devices", A. Perrig & L. van Doorn (2010). Original