Proposal Explorer

Add claims to see which ones the mechanisms address.

Not counted

Excluded by your filters: Timed challenge-response and memory-occupation challenges and Hardware-attested weight binding

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Timed challenge-response and memory-occupation challenges: Analysis · excluded by filters
• Hardware-attested weight binding: Independent red-team · excluded by filters

Excluded by your filters

• Timed challenge-response and memory-occupation challenges Prover cooperation is required; the filter allows partial at most.
• Hardware-attested weight binding Prover cooperation is required; the filter allows partial at most.

Open critical failures

• Underlying attestation can be forged or relayed in Hardware-attested weight binding

  Critical for weight binding against an operator with physical access to affected hardware, or with control of the hypervisor on an AMD SEV-SNP platform without AMD's fixes. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary.

  The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. ^{12 13 17 18 19 20}

  Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

  Known failure · Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this failure is mitigated. Add

Open significant failures

1 failure in 1 mechanism

• Remote memory narrows the timing margin in Timed challenge-response and memory-occupation challenges

  Data-centre remote memory access returns in about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview says verification of memory saturation depends on ruling out remote access by latency or physical disconnection. It names pre-staging data into local memory as the remaining evasion and proposes an unpredictable, capacity-filling challenge to close it. ¹

  Known failure · Theoretical argument · Significant · Open. On the record

  Related mechanism Research demo Bandwidth limits and compartmentalization: Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced. A pointer, not evidence that this failure is mitigated. Add

Scope limitations

• For private models, a user can confirm consistency but not content in Hardware-attested weight binding

  When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy. ^{11 22}

  Scope limitation · Open question. On the record

Open questions

• Error rates not quantified in Timed challenge-response and memory-occupation challenges

  Monfared et al. show separable timing distributions. Their acceptance rule passes a GPU when its mean time per round stays at or below a chosen maximum, and an appendix outlines statistical tests for the proof-of-work puzzle. They leave hardware-specific threshold values to future work and report no false-positive or false-negative rates. ³

  Open question · Open question. On the record

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors Add

  Excluded by filters: prover cooperation required

  • Bears on the open critical failure “Underlying attestation can be forged or relayed” in Hardware-attested weight binding. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
• Research demo Bandwidth limits and compartmentalization Add

  Excluded by filters: prover cooperation required

  • Bears on the open significant failure “Remote memory narrows the timing margin” in Timed challenge-response and memory-occupation challenges. Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced.
  • Timed challenge-response and memory-occupation challenges waits on it. Outside help, such as remote memory, must be excluded during challenges.
• Operational use TEE remote attestation for AI workloads Add

  Excluded by filters: prover cooperation required

  • Hardware-attested weight binding waits on it. Attestation that resists physical attackers, for the enclave variant.

Missing prerequisites

• Operational use TEE remote attestation for AI workloads needed by Hardware-attested weight binding Add

Blockers

4 blockers recorded

• Timed challenge-response and memory-occupation challenges
  • No network-level memory challenge across data-centre servers has been demonstrated. Adversarial validation ¹
  • Challenges that fill memory displace workloads; filling a pod's volatile memory takes tens of minutes and SSDs take hours. Performance & compatibility ^{1 3}
  • Outside help, such as remote memory, must be excluded during challenges. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization ¹
• Hardware-attested weight binding
  • Attestation that resists physical attackers, for the enclave variant. Hardware trust. Waits on TEE remote attestation for AI workloads ¹⁷

From the family or selected implementation's record. ?

Model weights

Hidden by Hardware-attested weight binding.

Not involved: Timed challenge-response and memory-occupation challenges.

Inputs and outputs

Not involved: Timed challenge-response and memory-occupation challenges.

Unspecified for Hardware-attested weight binding. Check the implementation record.

Training data

Not involved: Timed challenge-response and memory-occupation challenges and Hardware-attested weight binding.

Timed challenge-response and memory-occupation challenges

• Proposed Data-centre memory challenging Proposed architecture, Machine Intelligence Research Institute
• Research demo GPU contention probes Research prototype
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Research demo SAGE Research prototype
• Research demo VRAM-residency challenge Research prototype

Hardware-attested weight binding

• Research demo Attestable Audits Research prototype, University of Cambridge
• Research demo PAL*M Research prototype, University of Waterloo
• Operational use Tinfoil model identity (Modelwrap) Product, Tinfoil

1. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
2. Verification Plan, R. Dean (2026). Original
3. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
4. SAGE: Software-based Attestation for GPU Execution, A. Ivanov et al. (2023). Original
5. SWATT: SoftWare-based ATTestation for Embedded Devices, A. Seshadri et al. (2004). Original
6. Proofs of Space, S. Dziembowski et al. (2015). Original
7. Secure Code Update for Embedded Devices via Proofs of Secure Erasure, D. Perito & G. Tsudik (2010). Original
8. Software-Based Memory Erasure with Relaxed Isolation Requirements, S. Bursuc et al. (2024). Original
9. On the Difficulty of Software-Based Attestation of Embedded Devices, C. Castelluccia et al. (2009). Original
10. Refutation of "On the Difficulty of Software-Based Attestation of Embedded Devices", A. Perrig & L. van Doorn (2010). Original
11. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
12. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
13. A primer on secure enclaves, Tinfoil (2026). Original
14. Backend infrastructure, Tinfoil (2026). Original
15. How verification works in Tinfoil, Tinfoil (2026). Original
16. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). Original
17. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
18. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
19. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
20. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
21. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
22. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original