Proposal Explorer

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Excluded by your filters: Memory wiping and proofs of secure erasure

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Memory wiping and proofs of secure erasure: Analysis · excluded by filters

Excluded by your filters

• Memory wiping and proofs of secure erasure Attack testing is analysis; the filter asks for at least red-teamed.

Open significant flaws

2 flaws in 1 mechanism

• Memory the wipe cannot reach in Memory wiping and proofs of secure erasure

  Amodo's inventory of a GB200 system lists many memory stores beyond GPU HBM and host DRAM. It notes that SSD controller DRAM sits on a private bus that host commands cannot read or write, and that its optimized algorithm leaves 25 GiB of HBM unattested. It also asks how switch memory could be wiped. ^{5 6}

  Open question · Significant · Open. On the record

• Outside help during challenges in Memory wiping and proofs of secure erasure

  Classic proofs of secure erasure assume the device is isolated during the protocol. Bursuc et al. relax this to a bound on how close a helper can be, enforced by round-trip times. In data centres, remote memory access has round trips of about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview therefore says verification depends on ruling out RDMA by latency or physical disconnection. ^{3 4}

  Theoretical argument · Significant · Open. On the record

  Related mechanism R2 Timed challenge-response and memory-occupation challenges: Timed challenges bound how far away a helper can be by how quickly it must answer. A pointer, not evidence that this flaw is mitigated. Add

  Related mechanism R2 Bandwidth limits and compartmentalization: Removing or capping links between groups of accelerators limits remote memory access during a challenge. A pointer, not evidence that this flaw is mitigated. Add

Open minor flaws

1 mechanism with minor findings

• Gap between erased and total memory in Memory wiping and proofs of secure erasure

  Bursuc et al. note that memory left between the erased region and the device's full memory could hold data, and that their bounds are tighter only against a restricted adversary. ³

  Theoretical argument · Minor · Open. On the record

Not yet demonstrated

R1 Memory wiping and proofs of secure erasure

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R2 Bandwidth limits and compartmentalization Add

  Excluded by filters: attack testing: analysis

  • Bears on the open significant flaw “Outside help during challenges” in Memory wiping and proofs of secure erasure. Removing or capping links between groups of accelerators limits remote memory access during a challenge.
• R2 Timed challenge-response and memory-occupation challenges Add

  Excluded by filters: attack testing: analysis

  • Bears on the open significant flaw “Outside help during challenges” in Memory wiping and proofs of secure erasure. Timed challenges bound how far away a helper can be by how quickly it must answer.
  • Memory wiping and proofs of secure erasure waits on it. Timed challenges must exclude remote memory and other helpers.

Missing prerequisites

• R2 Timed challenge-response and memory-occupation challenges needed by Memory wiping and proofs of secure erasure Add

Blockers

3 blockers recorded

• Memory wiping and proofs of secure erasure
  • Wipes take time: tens of minutes for a pod's volatile memory and hours for SSDs, displacing work. Performance & compatibility ^{4 5 6}
  • Timed challenges must exclude remote memory and other helpers. Coverage & hidden compute. Waits on Timed challenge-response and memory-occupation challenges ^{3 4}
  • All memory stores in a system must be inventoried and wiped at the same time. Coverage & hidden compute ⁵

From the family or selected implementation's record. ?

Model weights

Not involved: Memory wiping and proofs of secure erasure.

Inputs and outputs

Not involved: Memory wiping and proofs of secure erasure.

Training data

Not involved: Memory wiping and proofs of secure erasure.

Memory wiping and proofs of secure erasure

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute

1. Verification Plan, R. Dean (2026). Original
2. Secure Code Update for Embedded Devices via Proofs of Secure Erasure, D. Perito & G. Tsudik (2010). Original
3. Software-Based Memory Erasure with Relaxed Isolation Requirements, S. Bursuc et al. (2024). Original
4. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
5. Memory Wipes - Performance Analysis, Amodo Design (2026). Original
6. Improving Disk Wiping Speed for Memory Wipes, Amodo Design (2026). Original
7. Amodo-Design/PoSE-Memory-Wiping (GitHub repository), Amodo Design (2026). Original
8. Empirical Evaluation of Memory-Erasure Protocols, R. Gil-Pons et al. (2025). Original