Proposal Explorer

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Excluded by your filters: On-chip telemetry from timing, memory and performance counters and Model identity attestation

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• On-chip telemetry from timing, memory and performance counters: Red-teamed · excluded by filters
• Model identity attestation: Independent red-team · excluded by filters

Excluded by your filters

• On-chip telemetry from timing, memory and performance counters Prover cooperation is partial; the filter allows not required.
• Model identity attestation Prover cooperation is required; the filter allows not required.

Open critical flaws

• Software-read telemetry can be forged by the operator in On-chip telemetry from timing, memory and performance counters

  NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized. ^{1 3}

  Theoretical argument · Critical · Open. On the record

  Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing. A pointer, not evidence that this flaw is mitigated. Add

• Underlying attestation can be forged or relayed in Model identity attestation

  Critical for the enclave route against an operator with physical access to affected hardware, or control of an unpatched SEV-SNP hypervisor. It does not apply to the recomputation route. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary.

  The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. ^{7 9 13 15 16 17}

  Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

  Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

  Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this flaw is mitigated. Add

Open significant flaws

5 flaws in 2 mechanisms

• Adversarially disguised fine-tuning partly evades classification in On-chip telemetry from timing, memory and performance counters

  Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware. ³

  Demonstrated attack · Significant · Open. On the record

• Timing challenges do not identify the individual chip in On-chip telemetry from timing, memory and performance counters

  GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use. ¹

  Theoretical argument · Significant · Open. On the record

• Counters leak information about protected workloads in On-chip telemetry from timing, memory and performance counters

  Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality. ^{4 5}

  Theoretical argument · Significant · Open. On the record

• For private models, a user can confirm consistency but not content in Model identity attestation

  When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy. ^{6 18}

  Open question · Significant · Open. On the record

• Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel in Model identity attestation

  The recomputation variant assumes that every input, output and seed is logged correctly, and that the attacker can neither predict nor manipulate which messages are sampled for verification. Legitimate nondeterminism concentrates at a few token positions, and slow leaks within the tolerated slack remain possible. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token, reducing the exfiltration slowdown from 146–254 times under benign prompts to 60–118 times. The attack targets the exfiltration bound, not the check that outputs match the declared model. ^{8 14}

  Demonstrated attack · Significant · Open. On the record

  Related mechanism R1 Network taps and certifiers: Taps are proposed to copy and hash traffic on the monitored links, reducing reliance on the prover's own log. This still depends on the monitored boundary and trusted capture. A pointer, not evidence that this flaw is mitigated. Add

  Related mechanism R3 Deterministic and bit-exact inference: Bit-exact inference would remove the numerical tolerance that leaves this channel. A pointer, not evidence that this flaw is mitigated. Add

Open minor flaws

1 mechanism with minor findings

• No quantified error rates or formal thresholds for timing primitives in On-chip telemetry from timing, memory and performance counters

  Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work. ¹

  Open question · Minor · Open. On the record

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R1 Hardware-enabled guarantees (flexHEG) and guarantee processors Add

  Excluded by filters: prover cooperation required

  • Bears on the open critical flaw “Software-read telemetry can be forged by the operator” in On-chip telemetry from timing, memory and performance counters. A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing.
  • Bears on the open critical flaw “Underlying attestation can be forged or relayed” in Model identity attestation. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
  • On-chip telemetry from timing, memory and performance counters waits on it. Shipping accelerators need a tamper-resistant, authenticated telemetry path.
• R3 Deterministic and bit-exact inference Add

  Excluded by filters: prover cooperation required

  • Bears on the open significant flaw “Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel” in Model identity attestation. Bit-exact inference would remove the numerical tolerance that leaves this channel.
  • Model identity attestation waits on it. Numerical nondeterminism limits how tightly recomputation can pin down the model and sampling.
• R1 Network taps and certifiers Add

  Excluded by filters: prover cooperation required

  • Bears on the open significant flaw “Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel” in Model identity attestation. Taps are proposed to copy and hash traffic on the monitored links, reducing reliance on the prover's own log. This still depends on the monitored boundary and trusted capture.
• R3 TEE remote attestation for AI workloads Add

  Excluded by filters: prover cooperation required

  • Model identity attestation waits on it. Attestation that resists physical attackers, for the enclave variant.
  • On-chip telemetry from timing, memory and performance counters depends on it.

Missing prerequisites

• R3 TEE remote attestation for AI workloads needed by On-chip telemetry from timing, memory and performance counters Add

Shared foundations

• TEE remote attestation for AI workloads relied on by On-chip telemetry from timing, memory and performance counters and Model identity attestation

Blockers

7 blockers recorded

• On-chip telemetry from timing, memory and performance counters
  • Shipping accelerators need a tamper-resistant, authenticated telemetry path. Hardware trust. Waits on Hardware-enabled guarantees (flexHEG) and guarantee processors ^{2 3}
  • NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. Privacy & leakage ^{4 5}
  • Continuous challenge puzzles cost power and throughput on production workloads. Performance & compatibility ¹
  • Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. Adversarial validation ³
• Model identity attestation
  • Attestation that resists physical attackers, for the enclave variant. Hardware trust. Waits on TEE remote attestation for AI workloads ¹³
  • Numerical nondeterminism limits how tightly recomputation can pin down the model and sampling. Protocol soundness. Waits on Deterministic and bit-exact inference ⁸
  • The recomputation variant needs the verifier to hold the declared weights. Access & governance ⁸

From the family or selected implementation's record. ?

Model weights

Depends on the design for On-chip telemetry from timing, memory and performance counters and Model identity attestation.

Inputs and outputs

Depends on the design for On-chip telemetry from timing, memory and performance counters and Model identity attestation.

Training data

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Model identity attestation.

On-chip telemetry from timing, memory and performance counters

None on the map

Model identity attestation

• R2 Attestable Audits Research prototype, University of Cambridge
• R2 PAL*M Research prototype, University of Waterloo
• R3 Tinfoil model identity (Modelwrap) Product, Tinfoil

1. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
2. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). Original
3. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). Original
4. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
5. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original
6. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
7. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
8. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
9. A primer on secure enclaves, Tinfoil (2026). Original
10. Backend infrastructure, Tinfoil (2026). Original
11. How verification works in Tinfoil, Tinfoil (2026). Original
12. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). Original
13. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
14. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
15. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
16. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
17. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
18. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original