Proposal Explorer

For the goal Enforce chip export controls. Each of its claims is marked direct or supporting.

Goal claims not in the proposal

• Chips are where they are declared to be Direct Add

Outside this map

• End-user and end-use verification. Avellar and Grunewald also cover end-user verification, such as know-your-customer checks, and end-use verification, such as audits of compute provisioning. This map has no records for these compliance processes. B. Avellar & E. Grunewald 2026

No new hardware needed

On-chip telemetry from timing, memory and performance counters

Not counted

Excluded by your filters: Safeguard attestation

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Safeguard attestation: Analysis · excluded by filters
• On-chip telemetry from timing, memory and performance counters: Red-teamed

Excluded by your filters

• Safeguard attestation Prover cooperation is required; the filter allows partial at most.

Open critical flaws

• Software-read telemetry can be forged by the operator in On-chip telemetry from timing, memory and performance counters

  NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized. ^{14 16}

  Theoretical argument · Critical · Open. On the record

  Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing. A pointer, not evidence that this flaw is mitigated. Add

Open significant flaws

8 flaws in 2 mechanisms

• Attestation shows a safeguard ran, not that it is effective in Safeguard attestation

  Proof of guardrail ensures that the guardrail executed, but the guardrail can still err or be jailbroken. Because the guardrail must be open source, a malicious developer can attack it with jailbreaks while still presenting a valid proof. In the authors' evaluation, Llama Guard 3 reached an F1 score of 0.56 on the unsafe class of the ToxicChat dataset. The authors state that proof of guardrail should not be interpreted or advertised as proof of safety. ¹

  Theoretical argument · Significant · Open. On the record

• Selective attestation leaves traffic uncovered in Safeguard attestation

  Attestations are issued per response. In the prototype, the agent offers them when it receives high-stakes questions, so nothing shows that unattested traffic went through the same path. PAL*M's authors note that a prover could cherry-pick favourable executions, and suggest verifier-published nonces or requesting only session-level proofs. A governance analysis notes that auditors also need assurance that all activity is accounted for, since a host could start a second confidential virtual machine that bypasses monitoring. ^{1 4 9}

  Theoretical argument · Significant · Open. On the record

  Related mechanism R2 On-chip telemetry from timing, memory and performance counters: On-chip counters are a proposed route to evidence about everything a chip runs, including a second virtual machine that skips the safeguard. A pointer, not evidence that this flaw is mitigated. In the proposal.

• Measurements may omit behaviour-relevant configuration or runtime changes in Safeguard attestation

  Every component that influences inference behaviour must be covered by the launch measurement, including feature flags, environment variables and invocation arguments. A launch measurement also does not show that a program keeps running as measured if the kernel is later compromised. ⁹

  Theoretical argument · Significant · Open. On the record

• Components outside the attested boundary in Safeguard attestation

  In the proof-of-guardrail experiments, the guardrail model and the agent's backend model were both reached through external APIs, and the authors leave the decision to trust those APIs to the verifier. The measured wrapper must also have no vulnerability that lets the unmeasured agent bypass the guardrail, for example by executing arbitrary commands inside the enclave. The code's README states that the enclave does not currently restrict the agent's arbitrary command execution, which could be used to bypass guardrails. ^{1 2}

  Theoretical argument · Significant · Open. On the record

• Memory-bus interposition extracts attestation keys and forges attestations in Safeguard attestation

  Applies to variants using the affected Intel or AMD trust roots. PAL*M excludes physical attacks. A TDX-backed safeguard claim against a physical host attacker would be defeated, but these studies do not demonstrate a break of the AWS Nitro proof-of-guardrail prototype or of verifier-side recomputation.

  The TEE findings cover DDR5 attacks on Intel TDX, the H100 relay demonstration, DDR4 attacks on AMD SEV-SNP, and software-only SEV-SNP forgery before AMD's fixes. These are inherited hardware limits; a governance analysis explains why physical access matters in a treaty setting. ^{1 4 7 8 9 10 11 12 13}

  Response: Intel and AMD place the physical attack class outside their threat models, according to the researchers. AMD reports firmware fixes for RMPocalypse.

  Demonstrated attack · Significant · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

  Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this flaw is mitigated. Add

• Adversarially disguised fine-tuning partly evades classification in On-chip telemetry from timing, memory and performance counters

  Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware. ¹⁶

  Demonstrated attack · Significant · Open. On the record

• Timing challenges do not identify the individual chip in On-chip telemetry from timing, memory and performance counters

  GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use. ¹⁴

  Theoretical argument · Significant · Open. On the record

• Counters leak information about protected workloads in On-chip telemetry from timing, memory and performance counters

  Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality. ^{9 17}

  Theoretical argument · Significant · Open. On the record

Open minor flaws

1 mechanism with minor findings

• No quantified error rates or formal thresholds for timing primitives in On-chip telemetry from timing, memory and performance counters

  Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work. ¹⁴

  Open question · Minor · Open. On the record

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R1 Hardware-enabled guarantees (flexHEG) and guarantee processors Add

  Excluded by filters: prover cooperation required

  • Bears on the open critical flaw “Software-read telemetry can be forged by the operator” in On-chip telemetry from timing, memory and performance counters. A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing.
  • Bears on the open significant flaw “Memory-bus interposition extracts attestation keys and forges attestations” in Safeguard attestation. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
  • On-chip telemetry from timing, memory and performance counters waits on it. Shipping accelerators need a tamper-resistant, authenticated telemetry path.
• R3 Model identity attestation Add

  Excluded by filters: prover cooperation required

  • Safeguard attestation waits on it. Safeguard evidence must be bound to the model actually served, which depends on model-identity attestation.
• R3 TEE remote attestation for AI workloads Add

  Excluded by filters: prover cooperation required

  • Safeguard attestation waits on it. Frontier model inference typically needs several GPUs, GPU confidential computing is less mature than CPU support, and CPU inference, which an enclave prototype had to use, ran about 100 times slower than GPU inference.
  • Safeguard attestation waits on it. Trust rests on a small number of hardware vendors, and a per-CPU Intel attestation key has been extracted by physical attack.
  • On-chip telemetry from timing, memory and performance counters depends on it.

Missing prerequisites

• R3 TEE remote attestation for AI workloads needed by Safeguard attestation and On-chip telemetry from timing, memory and performance counters Add
• R3 Model identity attestation needed by Safeguard attestation Add

Shared foundations

• TEE remote attestation for AI workloads relied on by Safeguard attestation and On-chip telemetry from timing, memory and performance counters

Blockers

9 blockers recorded

• Safeguard attestation
  • No published design shows that all of a provider's traffic passes through the attested safeguard path; current evidence covers individual attested responses. Coverage & hidden compute ^{1 9}
  • Frontier model inference typically needs several GPUs, GPU confidential computing is less mature than CPU support, and CPU inference, which an enclave prototype had to use, ran about 100 times slower than GPU inference. Performance & compatibility. Waits on TEE remote attestation for AI workloads ^{9 18}
  • Trust rests on a small number of hardware vendors, and a per-CPU Intel attestation key has been extracted by physical attack. Hardware trust. Waits on TEE remote attestation for AI workloads ^{7 9}
  • Safeguard evidence must be bound to the model actually served, which depends on model-identity attestation. Evidence binding. Waits on Model identity attestation ^{18 19}
  • No independent red-team or audit of a safeguard-attestation system has been published, and the available prototypes are described by their authors as proofs of concept that have not been stress-tested by a counterparty. Adversarial validation ^{2 6}
• On-chip telemetry from timing, memory and performance counters
  • Shipping accelerators need a tamper-resistant, authenticated telemetry path. Hardware trust. Waits on Hardware-enabled guarantees (flexHEG) and guarantee processors ^{15 16}
  • NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. Privacy & leakage ^{9 17}
  • Continuous challenge puzzles cost power and throughput on production workloads. Performance & compatibility ¹⁴
  • Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. Adversarial validation ¹⁶

From the family or selected implementation's record. ?

Model weights

Depends on the design for Safeguard attestation and On-chip telemetry from timing, memory and performance counters.

Inputs and outputs

Depends on the design for Safeguard attestation and On-chip telemetry from timing, memory and performance counters.

Training data

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Safeguard attestation.

Safeguard attestation

None on the map

On-chip telemetry from timing, memory and performance counters

None on the map

1. Proof-of-Guardrail in AI Agents and What (Not) to Trust from It, X. Jin et al. (2026). Original
2. Verifiable-ClawGuard: proof-of-guardrail reference code, SaharaLabsAI (2026). Original
3. Safety Without Compromising on Privacy, D. McCann-Sayles et al. (2026). Original
4. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
5. Enabling Verifiably-Scoped Monitoring through Large Language Models and Trusted Compute, B. Penchas et al. (2026). Original
6. Auditor-in-a-Box: Tools for Third-Party Auditing, R. Rinberg & B. Penchas (2026). Original
7. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
8. DDRop: Active Memory Interposer Attacks on Confidential VMs by Dropping DDR5 Writes, J. De Meulemeester et al. (2026). Original
9. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
10. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
11. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
12. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
13. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
14. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
15. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). Original
16. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). Original
17. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original
18. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original
19. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original