Proposal Explorer
ResetA verification proposal from the AI Verification Tech Map, from its records of 2026-10-08. https://trustbutveri.fyi/explorer/?mechanisms=M-0023,M-0012&coop=partial&hide=io
Analysis
Applied filters: Prover cooperation: Partial at most; Keep hidden from the verifier: inputs and outputs. Not set (Any): Prover, Verifier devices on site, Chips, Minimum readiness, Attack testing.
Overview
| Mechanism | Readiness | Open flaws |
|---|---|---|
| Safeguard attestation ⚠ excluded by your filters: prover cooperation required | R2 | 5 significant |
| Model identity attestation ⚠ excluded by your filters: prover cooperation required | R3 | 1 critical2 significant |
- Open flaws: n critical n significant n minor
- ⚠ Dimmed: excluded by your filters
Claim coverageNo claims yet
Add claims to see which ones the mechanisms address.
PropertiesNone recorded
- Not counted
- Excluded by your filters: Safeguard attestation and Model identity attestation
Attack testing2 mechanisms with published testing
Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.
- Safeguard attestation: Analysis · excluded by filters
- Model identity attestation: Independent red-team · excluded by filters
Limits1 mechanism with open critical findings · 2 excluded by filters · 2 mechanisms with open significant findings
- Excluded by your filters
- Safeguard attestation Prover cooperation is required; the filter allows partial at most.
- Model identity attestation Prover cooperation is required; the filter allows partial at most.
- Open critical flaws
Underlying attestation can be forged or relayed in Model identity attestation
Critical for the enclave route against an operator with physical access to affected hardware, or control of an unpatched SEV-SNP hypervisor. It does not apply to the recomputation route. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary.
The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. 4 7 10 11 12 16
Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.
Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads
Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this flaw is mitigated. Add
- Open significant flaws
7 flaws in 2 mechanisms
Attestation shows a safeguard ran, not that it is effective in Safeguard attestation
Proof of guardrail ensures that the guardrail executed, but the guardrail can still err or be jailbroken. Because the guardrail must be open source, a malicious developer can attack it with jailbreaks while still presenting a valid proof. In the authors' evaluation, Llama Guard 3 reached an F1 score of 0.56 on the unsafe class of the ToxicChat dataset. The authors state that proof of guardrail should not be interpreted or advertised as proof of safety. 1
Theoretical argument · Significant · Open. On the record
Selective attestation leaves traffic uncovered in Safeguard attestation
Attestations are issued per response. In the prototype, the agent offers them when it receives high-stakes questions, so nothing shows that unattested traffic went through the same path. PAL*M's authors note that a prover could cherry-pick favourable executions, and suggest verifier-published nonces or requesting only session-level proofs. A governance analysis notes that auditors also need assurance that all activity is accounted for, since a host could start a second confidential virtual machine that bypasses monitoring. 1 4 9
Theoretical argument · Significant · Open. On the record
Related mechanism R2 On-chip telemetry from timing, memory and performance counters: On-chip counters are a proposed route to evidence about everything a chip runs, including a second virtual machine that skips the safeguard. A pointer, not evidence that this flaw is mitigated. Add
Measurements may omit behaviour-relevant configuration or runtime changes in Safeguard attestation
Every component that influences inference behaviour must be covered by the launch measurement, including feature flags, environment variables and invocation arguments. A launch measurement also does not show that a program keeps running as measured if the kernel is later compromised. 9
Theoretical argument · Significant · Open. On the record
Components outside the attested boundary in Safeguard attestation
In the proof-of-guardrail experiments, the guardrail model and the agent's backend model were both reached through external APIs, and the authors leave the decision to trust those APIs to the verifier. The measured wrapper must also have no vulnerability that lets the unmeasured agent bypass the guardrail, for example by executing arbitrary commands inside the enclave. The code's README states that the enclave does not currently restrict the agent's arbitrary command execution, which could be used to bypass guardrails. 1 2
Theoretical argument · Significant · Open. On the record
Memory-bus interposition extracts attestation keys and forges attestations in Safeguard attestation
Applies to variants using the affected Intel or AMD trust roots. PAL*M excludes physical attacks. A TDX-backed safeguard claim against a physical host attacker would be defeated, but these studies do not demonstrate a break of the AWS Nitro proof-of-guardrail prototype or of verifier-side recomputation.
The TEE findings cover DDR5 attacks on Intel TDX, the H100 relay demonstration, DDR4 attacks on AMD SEV-SNP, and software-only SEV-SNP forgery before AMD's fixes. These are inherited hardware limits; a governance analysis explains why physical access matters in a treaty setting. 1 4 7 8 9 10 11 12 13
Response: Intel and AMD place the physical attack class outside their threat models, according to the researchers. AMD reports firmware fixes for RMPocalypse.
Demonstrated attack · Significant · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads
Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this flaw is mitigated. Add
For private models, a user can confirm consistency but not content in Model identity attestation
When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy. 14 21
Open question · Significant · Open. On the record
Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel in Model identity attestation
The recomputation variant assumes that every input, output and seed is logged correctly, and that the attacker can neither predict nor manipulate which messages are sampled for verification. Legitimate nondeterminism concentrates at a few token positions, and slow leaks within the tolerated slack remain possible. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token, reducing the exfiltration slowdown from 146–254 times under benign prompts to 60–118 times. The attack targets the exfiltration bound, not the check that outputs match the declared model. 15 20
Demonstrated attack · Significant · Open. On the record
Related mechanism R1 Network taps and certifiers: Taps are proposed to copy and hash traffic on the monitored links, reducing reliance on the prover's own log. This still depends on the monitored boundary and trusted capture. A pointer, not evidence that this flaw is mitigated. Add
Related mechanism R3 Deterministic and bit-exact inference: Bit-exact inference would remove the numerical tolerance that leaves this channel. A pointer, not evidence that this flaw is mitigated. Add
Possible additions4 for open flaws · 2 for dependencies
Mechanisms on the map that are not in the proposal. Pointers, not recommendations.
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- Bears on the open significant flaw “Selective attestation leaves traffic uncovered” in Safeguard attestation. On-chip counters are a proposed route to evidence about everything a chip runs, including a second virtual machine that skips the safeguard.
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Excluded by filters: prover cooperation required
- Bears on the open critical flaw “Underlying attestation can be forged or relayed” in Model identity attestation. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
- Bears on the open significant flaw “Memory-bus interposition extracts attestation keys and forges attestations” in Safeguard attestation. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
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Excluded by filters: prover cooperation required
- Bears on the open significant flaw “Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel” in Model identity attestation. Bit-exact inference would remove the numerical tolerance that leaves this channel.
- Model identity attestation waits on it. Numerical nondeterminism limits how tightly recomputation can pin down the model and sampling.
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Excluded by filters: prover cooperation required
- Bears on the open significant flaw “Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel” in Model identity attestation. Taps are proposed to copy and hash traffic on the monitored links, reducing reliance on the prover's own log. This still depends on the monitored boundary and trusted capture.
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Excluded by filters: prover cooperation required
- Safeguard attestation waits on it. Frontier model inference typically needs several GPUs, GPU confidential computing is less mature than CPU support, and CPU inference, which an enclave prototype had to use, ran about 100 times slower than GPU inference.
- Safeguard attestation waits on it. Trust rests on a small number of hardware vendors, and a per-CPU Intel attestation key has been extracted by physical attack.
- Model identity attestation waits on it. Attestation that resists physical attackers, for the enclave variant.
Dependencies1 missing prerequisite · 1 shared foundation · 8 blockers
- Missing prerequisites
- R3 TEE remote attestation for AI workloads needed by Safeguard attestation Add
- Shared foundations
- TEE remote attestation for AI workloads relied on by Safeguard attestation and Model identity attestation
- Blockers
8 blockers recorded
- Safeguard attestation
- No published design shows that all of a provider's traffic passes through the attested safeguard path; current evidence covers individual attested responses. Coverage & hidden compute 1 9
- Frontier model inference typically needs several GPUs, GPU confidential computing is less mature than CPU support, and CPU inference, which an enclave prototype had to use, ran about 100 times slower than GPU inference. Performance & compatibility. Waits on TEE remote attestation for AI workloads 9 21
- Trust rests on a small number of hardware vendors, and a per-CPU Intel attestation key has been extracted by physical attack. Hardware trust. Waits on TEE remote attestation for AI workloads 7 9
- Safeguard evidence must be bound to the model actually served, which depends on model-identity attestation. Evidence binding. Waits on Model identity attestation 14 21
- No independent red-team or audit of a safeguard-attestation system has been published, and the available prototypes are described by their authors as proofs of concept that have not been stress-tested by a counterparty. Adversarial validation 2 6
- Model identity attestation
- Attestation that resists physical attackers, for the enclave variant. Hardware trust. Waits on TEE remote attestation for AI workloads 7
- Numerical nondeterminism limits how tightly recomputation can pin down the model and sampling. Protocol soundness. Waits on Deterministic and bit-exact inference 15
- The recomputation variant needs the verifier to hold the declared weights. Access & governance 15
- Safeguard attestation
What the verifier sees2 depend on design
From the family or selected implementation's record.
- Model weights
Depends on the design for Safeguard attestation and Model identity attestation.
- Inputs and outputs
Depends on the design for Safeguard attestation and Model identity attestation.
- Training data
Not involved: Safeguard attestation and Model identity attestation.
Exposure notes
- Safeguard attestation: The enclave route signs hashes of the safeguard, request and response; a low-trust design has the verifier re-run and screen sampled requests itself.
- Model identity attestation: The enclave route shows only hashes; the recomputation route gives the verifier the weights and the sampled requests and responses.
Implementations3 systems
- Safeguard attestation
- None on the map
- Model identity attestation
- R2 Attestable Audits Research prototype, University of Cambridge
- R2 PAL*M Research prototype, University of Waterloo
- R3 Tinfoil model identity (Modelwrap) Product, Tinfoil
Sources21 cited
- Proof-of-Guardrail in AI Agents and What (Not) to Trust from It, X. Jin et al. (2026). Original
- Verifiable-ClawGuard: proof-of-guardrail reference code, SaharaLabsAI (2026). Original
- Safety Without Compromising on Privacy, D. McCann-Sayles et al. (2026). Original
- PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
- Enabling Verifiably-Scoped Monitoring through Large Language Models and Trusted Compute, B. Penchas et al. (2026). Original
- Auditor-in-a-Box: Tools for Third-Party Auditing, R. Rinberg & B. Penchas (2026). Original
- TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
- DDRop: Active Memory Interposer Attacks on Confidential VMs by Dropping DDR5 Writes, J. De Meulemeester et al. (2026). Original
- On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
- Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
- RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
- SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
- A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
- How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
- Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
- A primer on secure enclaves, Tinfoil (2026). Original
- Backend infrastructure, Tinfoil (2026). Original
- How verification works in Tinfoil, Tinfoil (2026). Original
- modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). Original
- Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
- Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original
Share the link to this proposal. This proposal is also available as plain text and JSON.
Filter mechanisms
Filters apply to mechanisms only. They describe the setting a proposal is for, and all are off by default. A mechanism that a filter rules out is flagged and does not count towards claim coverage. Selected implementations use their own record fields. A match means not excluded; conditional or unspecified exposure stays with a note. Passing a filter does not establish that the assumptions hold in a deployment.
6 of 25 mechanisms match · Clear all
Prover
How far can the party being checked be trusted?
The prover is the party being checked. Semi-trusted designs rely on part of its stack: usually the chip vendor's hardware root of trust, its firmware or counters, or its supply-chain records. Adversarial designs aim to hold even if it cheats wherever the checks allow, within their stated assumptions.
Keeps mechanisms whose threat model holds against at least this prover. Adversarial is the strongest assumption. Definitions
Verifier devices on site
May the verifier install its own hardware at the prover's sites?
Some mechanisms need a device the verifier owns or trusts at the prover's facility, such as a network tap, a bandwidth limiter or a sealed sensor. Choose Not allowed when the setting rules that out. Inspectors are not covered.
"Not allowed" removes mechanisms that need a retrofit device, such as a network tap or a sealed sensor. Definitions
Prover cooperation
How much must the prover take part?
Required: the prover takes part, for example by logging requests, producing proofs or opening records. Partial: some access, such as installing a device. Not required: works from outside, such as satellite imagery.
"Partial at most" removes mechanisms that need the prover's active participation. "Not required" keeps only those that work without it. Definitions
Chips
May the proposal depend on new chip designs?
New chip features take years to reach a deployed fleet and cover only chips made after they ship. Mechanisms that use shipping features, such as trusted execution environments or performance counters, stay.
"Existing chips only" removes mechanisms that need changes to future chip designs. Definitions
Minimum readiness
How mature must each mechanism be?
- Any (selected)6 match
- R1 Proposed6 match
- R2 Demonstrated3 match
- R3 In production0 match
- R4 Deployment-ready0 match
A level describes the public evidence for a mechanism's stated use, not its cost or feasibility. R3 can still have open critical flaws.
Keeps mechanisms whose readiness level is at least this one. Definitions
Attack testing
How hard has each mechanism been attacked in public?
The strongest published attempt to break the mechanism for its verification use: a security analysis, red-teaming by its developers or collaborators, or a red team independent of them.
Keeps mechanisms whose strongest published attack testing is at least this. Definitions
Keep hidden from the verifier
What must the verifier never see? Choose any.
Model weights: the checked model's parameters. Inputs and outputs: the requests a deployed model serves and its responses. Training data: what a model was trained on. Each mechanism's exposure is the editors' reading of its record: shown, depends on the design (kept, with a note), hidden, not involved, or unspecified for a selected implementation. Code and configuration are not covered yet.
Removes mechanisms that show the asset to the verifier. Conditional or unspecified exposure stays with a note and needs checking against the privacy requirement.
Claims
A claim is something one party wants to verify about another party's AI hardware or software. Each claim's number shows how the proposal addresses it.
- Addressed. A mechanism in the proposal is aimed at this claim and is not excluded by the filters.
- Partly addressed. Only supporting mechanisms, or mechanisms aimed at it that the filters exclude.
- Unaddressed. No mechanism in the proposal addresses this claim.
Addressed means a mechanism in the proposal is aimed at the claim and is not excluded by your filters. It does not mean the claim is verified: check its assessed use, readiness, assumptions and open flaws.
Mechanisms
A mechanism is a general technique for verifying claims. Its badge is its readiness level for its stated use. An optional implementation choice narrows its assumptions, assessed use and claim links to that record. Lines join it to the claims it addresses. Click a line for details.Under its name it lists the claims it is aimed at or supports.
- Aimed at the claim: verifying it is a direct purpose of the mechanism.
- Supports the claim: helps verify it without being aimed at it.
- Faint: excluded by your filters, so it does not count towards claim coverage.
Overview
One row per mechanism in the proposal. Every mark comes from that mechanism's record, as listed in the panels below; what the verifier sees is the editors' reading of the record's text. Flaw counts are per mechanism. Summary counts name mechanisms with open findings, not a sum of attacks. Choosing an implementation narrows each row to that record's assessed use; family findings remain as context.
What the verifier sees
For model weights, inputs and outputs, and training data. This is the editors' reading of each mechanism's record (its threat model, how it works and its limitations), not a field of the record. Shown: the verifier sees it. Depends: on the design or variant, or the verifier sees only samples. Hidden: the verifier sees only commitments, hashes, proofs or results. Not involved: the record does not handle it. Unspecified: the selected implementation has no asset-specific assessment here.
Possible additions
Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open flaw or a dependency. They are pointers, not recommendations: each brings its own readiness level and flaws, and none is claimed to close a flaw. Links from flaws are the editors' reading of the two records.
Start from a goal
A goal is something a rule or agreement about AI sets out to achieve. Choosing one loads the claims it needs verified. Your mechanisms and filters stay as they are.
- Cap frontier training2 direct, 3 supportingKeep every AI training run below an agreed amount of compute.
- Pause frontier AI development2 direct, 3 supportingStop new AI training runs and experiments for an agreed period, while existing models stay in service.
- Deploy only evaluated models2 direct, 3 supportingDeploy powerful AI models widely only after their risks have been evaluated and judged manageable.
- Prevent catastrophic misuse2 direct, 2 supportingKeep capable AI models from helping anyone carry out catastrophic attacks, such as biological or chemical ones.
- Prevent weight theft1 direct, 1 supportingKeep the weights of capable AI models from being copied out of the facilities that hold them.
- Enforce chip export controls1 directKeep export-controlled AI chips at the destinations they were authorised for.
Start from a published design
Choosing a design loads the mechanisms its record realises or depends on. If the proposal has no claims yet, it also loads the claims that record says the design addresses.
- AI 2040 inference-only verification stack7 mechanismsProposed architecture, AI Futures Project
- Low-trust AI compute verification system overview7 mechanismsProposed architecture, Machine Intelligence Research Institute
- RAND secure inference data center (SIDC) design3 mechanismsProposed architecture, RAND