Proposal Explorer

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Excluded by your filters: Bounding unexplained information in outputs, Chip location verification and Bandwidth limits and compartmentalization

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Bounding unexplained information in outputs: Independent red-team · excluded by filters
• Chip location verification: Analysis · excluded by filters
• Bandwidth limits and compartmentalization: Analysis · excluded by filters

Excluded by your filters

• Bounding unexplained information in outputs Prover cooperation is required; the filter allows partial at most.
• Chip location verification Prover cooperation is required; the filter allows partial at most.
• Bandwidth limits and compartmentalization Prover cooperation is required; the filter allows partial at most.

Open significant flaws

13 flaws in 3 mechanisms

• Prompt-controlled entropy inflation widens the covert channel in Bounding unexplained information in outputs

  Gumbel-based inference verification tolerates token choices that honest GPU nondeterminism could produce, and the size of that tolerated set grows with the model's output entropy. Kezins, an independent researcher, showed that an adversary who controls the prompt distribution can raise output entropy and roughly double the bits leaked per token. Across six models of 1 to 32 billion parameters, this cut the slowdown from 146–254 times under benign prompts to 60–118 times. Kezins argues that architectures built on the same unexplained-information bound inherit this attack surface, and recommends calibrating tolerances against local token entropy rather than benign traffic. ^{2 3}

  Demonstrated attack · Significant · Open. On the record

  Related mechanism R3 Deterministic and bit-exact inference: Bit-exact replay would remove the tolerance for numerical noise that sets the size of this channel. The record notes that it needs full hardware and software metadata. A pointer, not evidence that this flaw is mitigated. Add

• Information the declared computation explains is not bounded in Bounding unexplained information in outputs

  The bound limits unexplained bits only. Outputs that the declared computation fully explains can still carry valuable information: a compression study notes that an adversary with inference access can extract more proprietary information per bit than naive transmission allows. ^{1 4}

  Theoretical argument · Significant · Open. On the record

• Channels other than checked outputs are outside the bound in Bounding unexplained information in outputs

  The inference-verification scheme treats side channels as out of scope. A low-trust system design argues that suppressing physical covert bandwidth below kilobits per second is much more achievable than aiming for zero, and that a malicious device can leak one bit of information by deliberately outputting a wrong result. ^{2 5}

  Theoretical argument · Significant · Open. On the record

  Related mechanism R1 Side-channel suppression for isolated facilities: Physical side channels need separate suppression, which is this mechanism's purpose. A pointer, not evidence that this flaw is mitigated. Add

• The facility-level design is untested in Bounding unexplained information in outputs

  The compute-verification architecture is described with protocol details, potential attacks and prototyping plans, but no prototype results have been published. ¹

  Open question · Significant · Open. On the record

• Extracting a chip's key lets another device answer for it in Chip location verification

  Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM. ^{6 11}

  Theoretical argument · Significant · Open. On the record

• Added delay can shift an estimated position in Chip location verification

  Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location. ^{6 9}

  Demonstrated attack · Significant · Open. On the record

• Faster-than-assumed network paths in Chip location verification

  Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often. ^{6 9}

  Theoretical argument · Significant · Open. On the record

• Compromised landmarks can falsify measurements in Chip location verification

  A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators. ^{6 9 10}

  Theoretical argument · Significant · Open. On the record

• Low-communication training reduces the bandwidth training needs in Bandwidth limits and compartmentalization

  DiLoCo matched fully synchronous training on 8 workers while communicating 500 times less. Rahman writes that this family of methods theoretically allows large-scale training with less than 100 Mbps. Lucid includes these methods in its bounds, but notes that extreme activation compression, architectures with unusually small inter-layer widths, or modular paradigms could erode the margin. ^{14 17 18}

  Theoretical argument · Significant · Open. On the record

• Operator control of pod routing collapses the bound in Bandwidth limits and compartmentalization

  Lucid's analysis finds that if the operator can freely assign pods to routers, it could dedicate a whole cell of 100 or more pods to one pipeline stage. The bound then falls to about 90–220x uncompressed and as low as about 25x with compression. The proposed mitigation, auditor-controlled random assignment that is periodically re-randomized, has not been implemented. ¹⁴

  Theoretical argument · Significant · Open. On the record

• Undeclared local storage raises per-pod capacity in Bandwidth limits and compartmentalization

  More memory or storage per pod helps an adversary. Lucid requires per-pod storage to be declared, capped and physically inspected. ¹⁴

  Theoretical argument · Significant · Open. On the record

• Training within one pod is not covered in Bandwidth limits and compartmentalization

  Lucid's bounds concern pre-training models larger than the pods are sized for. Training models that fit in one pod, fine-tuning and reinforcement-learning post-training within one pod are outside the modelled threat. ¹⁴

  Open question · Significant · Open. On the record

• Parallel scale-up switches are hard enforcement points in Bandwidth limits and compartmentalization

  In GB200 topologies, GPUs reach GPUs in other nodes through NVSwitches without a NIC on the path. Amodo notes that limits are hard to enforce there because many switches work in parallel, so compromising one or two would bypass the limit. ¹⁶

  Theoretical argument · Significant · Open. On the record

Not yet demonstrated

R1 Chip location verification

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R1 Side-channel suppression for isolated facilities Add
  • Bears on the open significant flaw “Channels other than checked outputs are outside the bound” in Bounding unexplained information in outputs. Physical side channels need separate suppression, which is this mechanism's purpose.
  • Bounding unexplained information in outputs waits on it. Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target.
• R2 Tamper evidence for verifier devices Add
  • Bandwidth limits and compartmentalization waits on it. Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU.
• R3 Deterministic and bit-exact inference Add

  Excluded by filters: prover cooperation required

  • Bears on the open significant flaw “Prompt-controlled entropy inflation widens the covert channel” in Bounding unexplained information in outputs. Bit-exact replay would remove the tolerance for numerical noise that sets the size of this channel. The record notes that it needs full hardware and software metadata.
  • Bounding unexplained information in outputs waits on it. Tolerance for numerical nondeterminism sets the size of the residual channel; bit-exact replay would remove it but needs full hardware and software metadata.
• R1 Network taps and certifiers Add

  Excluded by filters: prover cooperation required

  • Bandwidth limits and compartmentalization waits on it. The verifier must know that all traffic leaving a pod crosses the capped, monitored links.
  • Bounding unexplained information in outputs depends on it.
• R3 Sampled inference recomputation Add

  Excluded by filters: prover cooperation required

  • Bounding unexplained information in outputs depends on it.
• R3 TEE remote attestation for AI workloads Add

  Excluded by filters: assumes a semi-trusted prover; prover cooperation required

  • Chip location verification depends on it.

Missing prerequisites

• R3 Sampled inference recomputation needed by Bounding unexplained information in outputs Add
• R1 Side-channel suppression for isolated facilities needed by Bounding unexplained information in outputs Add
• R1 Network taps and certifiers needed by Bounding unexplained information in outputs Add
• R3 TEE remote attestation for AI workloads needed by Chip location verification Add
• R2 Tamper evidence for verifier devices needed by Bandwidth limits and compartmentalization Add

Shared foundations

• Network taps and certifiers relied on by Bounding unexplained information in outputs and Bandwidth limits and compartmentalization

Blockers

13 blockers recorded

• Bounding unexplained information in outputs
  • The prover's compute must be isolated so that all traffic passes through the verifier's interlock; any unmonitored path voids the bound. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization ¹
  • Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ^{2 5}
  • Tolerance for numerical nondeterminism sets the size of the residual channel; bit-exact replay would remove it but needs full hardware and software metadata. Protocol soundness. Waits on Deterministic and bit-exact inference ^{3 5}
  • Recomputation over confidential weights and inputs needs a protected setting: prover recomputation in a verifier-controlled enclosure, verifier recomputation in a prover-controlled enclosure, or zero-knowledge proofs. Privacy & leakage ¹
  • No prototype of the facility-level architecture exists to red-team. Adversarial validation ¹
• Chip location verification
  • No public code or reproducible end-to-end location results are available for the reported H100 prototype. Adversarial validation ^{7 8}
  • Per-chip keys must be provisioned and protected against extraction; hardware-integrated, tamper-resistant versions still need R&D. Hardware trust ^{6 11 19}
  • The time limit forces a trade-off: a limit at the speed of light in fibre can be beaten by faster links, while one at the vacuum speed of light makes honest chips fail often. Protocol soundness ⁶
  • A trusted landmark network must be built and secured, and who should operate it, under what oversight, is unsettled. Access & governance ^{6 9}
• Bandwidth limits and compartmentalization
  • No cap that a verifier can check has been implemented or red-teamed. Adversarial validation ¹⁴
  • The verifier must know that all traffic leaving a pod crosses the capped, monitored links. Coverage & hidden compute. Waits on Network taps and certifiers ⁵
  • Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU. Hardware trust. Waits on Tamper evidence for verifier devices ^{14 16}
  • Advances in low-communication training could shrink the margin that the cap enforces. Capacity bounds ^{14 17 18}

From the family or selected implementation's record. ?

Model weights

Depends on the design for Bounding unexplained information in outputs.

Not involved: Chip location verification and Bandwidth limits and compartmentalization.

Inputs and outputs

Depends on the design for Bounding unexplained information in outputs.

Not involved: Chip location verification and Bandwidth limits and compartmentalization.

Training data

Not involved: Bounding unexplained information in outputs, Chip location verification and Bandwidth limits and compartmentalization.

Bounding unexplained information in outputs

None on the map

Chip location verification

• R1 Lucid sovereignty (location) certificates Standard, Lucid Computing

Bandwidth limits and compartmentalization

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 RAND secure inference data center (SIDC) design Proposed architecture, RAND

1. Verifying AI Compute by Bounding Unexplained Information Exfiltration, J. Petrie & Y. Mühlhäuser (2026). Original
2. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
3. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
4. Haiku to Opus in Just 10 bits: LLMs Unlock Large Compression Gains, R. Rinberg et al. (2026). Original
5. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
6. Location Verification for AI Chips, A. Brass & O. Aarne (2024). Original
7. Location Verification for AI Chips (issue brief), A. Brass (2025). Original
8. Ping-based Location, Ulyssean (2025). Original
9. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
10. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). Original
11. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). Original
12. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
13. Verification Plan, R. Dean (2026). Original
14. Traffic Shaping for Workload Classification, Lucid Computing (2026). Original
15. De-risking Interconnect Limits for AI Verification, A. Scher et al. (2026). Original
16. The Tray as a Bandwidth Boundary, Amodo Design (2026). Original
17. DiLoCo: Distributed Low-Communication Training of Language Models, A. Douillard et al. (2024). Original
18. Does Distributed Training Undermine Compute Governance?, R. Rahman (2026). Original
19. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original