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A verification proposal from the AI Verification Tech Map, from its records of 2026-10-08. https://trustbutveri.fyi/explorer/?mechanisms=M-0022&implementations=M-0022:I-0012&tested=red-teamed

Claims

Mechanisms1

Filters:× 7 of 25 match

Analysis

Overview

Columns Claims Prover Attack testing Hardware Verifier sees
MechanismReadinessOpen flaws
Side-channel suppression for isolated facilitiesLow-trust AI compute verification system overview ⚠ R121Family context below
  • Open flaws: n critical n significant n minor
  • ⚠ Dimmed: excluded by your filters; point at ⚠ for the reason
Claim coverageNo claims yet

Add claims to see which ones the mechanisms address.

PropertiesNone recorded
Not counted
Excluded by your filters: Side-channel suppression for isolated facilities
Attack testing1 mechanism with published testing

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

Limits1 family with findings to check · 1 excluded by filters · 1 not yet demonstrated · 1 mechanism with open significant findings
Excluded by your filters
Family findings
  • Side-channel suppression for isolated facilities

    Context for Low-trust AI compute verification system overview. These findings concern the family or other implementations; applicability must be checked against their stated scope.

    • Supply-chain implants may evade inspection in Side-channel suppression for isolated facilities

      Cankaya identifies malicious hardware embedded deep in purchased components as a residual risk that visual inspection and disassembly may not catch. He notes that radiographic examination under high-security standards could mitigate it. 3

      Theoretical argument · Significant · Open. On the record

    • Openings for airflow, power and optics weaken shielding in Side-channel suppression for isolated facilities

      Cankaya notes that keeping attenuation high while passing high-power airflow, cabling and optical links adds complexity beyond existing shielded-enclosure specifications. 3

      Theoretical argument · Significant · Open. On the record

    • Inspection assumptions may not hold in Side-channel suppression for isolated facilities

      The design's statistical argument assumes that visual or disassembly inspection catches every flaw that is present in a sampled unit. Cankaya is unsure whether destructive teardowns are defence-dominant or offence-dominant. 3

      Open question · Significant · Open. On the record

Open significant flaws
2 flaws in 1 mechanism
  • Mismatches cannot be attributed to cheating or error in Low-trust AI compute verification system overview

    A failed hash or replay does not show whether it came from an evasion attempt, a random bit flip or an evaluation error. The author notes that if detected anomalies can plausibly be waved off as malfunctions, deterrence becomes less effective, so the parties need an agreed escalation procedure that ends in attribution. 1

    Theoretical argument · Significant · Open. On the record

  • Inspector agents may be manipulable in Low-trust AI compute verification system overview

    Automated compliance screening with LLM-based inspector agents must resist prompt-injection attacks. Adversarially trained systems might hide malicious actions with steganography, which makes backdoor detection an open problem. 1

    Open question · Significant · Open. On the record

Open minor flaws
1 mechanism with minor findings
  • Deliberate faults leak a bit each in Low-trust AI compute verification system overview

    A malicious device can leak one bit by deliberately outputting a wrong result, which blocks a disclosure when the cross-comparison fails. The design therefore needs a pre-agreed budget of tolerated faults. 1

    Theoretical argument · Minor · Open. On the record

Possible additions4 for dependencies

Mechanisms on the map that are not in the proposal. Pointers, not recommendations.

  • R3 Deterministic and bit-exact inference Add

    Excluded by filters: attack testing: analysis

    • Side-channel suppression for isolated facilities waits on it. Exact replay needs complete hardware and software metadata, and the tolerable slowdown from emulation is an open question.
  • R2 Tamper evidence for verifier devices Add

    Excluded by filters: attack testing: analysis

    • Side-channel suppression for isolated facilities waits on it. Tamper-evident, rapidly mass-manufacturable and retrofittable enclosures for side-channel defence are an open research question, and physical security against covert communication in every monitored data centre is challenging.
  • R2 Timed challenge-response and memory-occupation challenges Add

    Excluded by filters: attack testing: analysis

    • Side-channel suppression for isolated facilities waits on it. Distinguishing one server's DRAM contents from another's by challenge-response timing, and a general challenge-response protocol for diverse data types, are open.
  • R1 Network taps and certifiers Add

    Excluded by filters: attack testing: analysis

    • Side-channel suppression for isolated facilities waits on it. Empirical feasibility of passive optical splitting at 53–112 GBaud under realistic conditions is an open question.
Dependencies2 missing prerequisites · 6 blockers
Missing prerequisites
Blockers
6 blockers recorded
  • Side-channel suppression for isolated facilities
    • Empirical feasibility of passive optical splitting at 53–112 GBaud under realistic conditions is an open question. Performance & compatibility. Waits on Network taps and certifiers 1
    • Exact replay needs complete hardware and software metadata, and the tolerable slowdown from emulation is an open question. Performance & compatibility. Waits on Deterministic and bit-exact inference 1
    • Tamper-evident, rapidly mass-manufacturable and retrofittable enclosures for side-channel defence are an open research question, and physical security against covert communication in every monitored data centre is challenging. Hardware trust. Waits on Tamper evidence for verifier devices 1
    • A mass-manufacturable, good-enough side-channel defence, particularly power-line filtering, has not been constructed or red-teamed. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities 1
    • Distinguishing one server's DRAM contents from another's by challenge-response timing, and a general challenge-response protocol for diverse data types, are open. Coverage & hidden compute. Waits on Timed challenge-response and memory-occupation challenges 1
    • The threat model is under-developed and needs input from cybersecurity and AI threat-modelling experts. Adversarial validation 1
What the verifier sees1 unspecified

From the family or selected implementation's record.

Model weights

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Inputs and outputs

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Training data

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Exposure notes
Implementations3 systems
Side-channel suppression for isolated facilities
Sources3 cited
  1. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
  2. Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors, N. Cankaya et al. (2026). Original
  3. Suppressing Side Channels in an Untrusted Data Center via Retrofitted Defenses, N. Cankaya (2026). Original

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Filter mechanisms

Filters apply to mechanisms only. They describe the setting a proposal is for, and all are off by default. A mechanism that a filter rules out is flagged and does not count towards claim coverage. Selected implementations use their own record fields. A match means not excluded; conditional or unspecified exposure stays with a note. Passing a filter does not establish that the assumptions hold in a deployment.

7 of 25 mechanisms match · Clear all

Prover

How far can the party being checked be trusted?

The prover is the party being checked. Semi-trusted designs rely on part of its stack: usually the chip vendor's hardware root of trust, its firmware or counters, or its supply-chain records. Adversarial designs aim to hold even if it cheats wherever the checks allow, within their stated assumptions.

Keeps mechanisms whose threat model holds against at least this prover. Adversarial is the strongest assumption. Definitions

Verifier devices on site

May the verifier install its own hardware at the prover's sites?

Some mechanisms need a device the verifier owns or trusts at the prover's facility, such as a network tap, a bandwidth limiter or a sealed sensor. Choose Not allowed when the setting rules that out. Inspectors are not covered.

"Not allowed" removes mechanisms that need a retrofit device, such as a network tap or a sealed sensor. Definitions

Prover cooperation

How much must the prover take part?

Required: the prover takes part, for example by logging requests, producing proofs or opening records. Partial: some access, such as installing a device. Not required: works from outside, such as satellite imagery.

"Partial at most" removes mechanisms that need the prover's active participation. "Not required" keeps only those that work without it. Definitions

Chips

May the proposal depend on new chip designs?

New chip features take years to reach a deployed fleet and cover only chips made after they ship. Mechanisms that use shipping features, such as trusted execution environments or performance counters, stay.

"Existing chips only" removes mechanisms that need changes to future chip designs. Definitions

Minimum readiness

How mature must each mechanism be?

A level describes the public evidence for a mechanism's stated use, not its cost or feasibility. R3 can still have open critical flaws.

Keeps mechanisms whose readiness level is at least this one. Definitions

Attack testing

How hard has each mechanism been attacked in public?

The strongest published attempt to break the mechanism for its verification use: a security analysis, red-teaming by its developers or collaborators, or a red team independent of them.

Keeps mechanisms whose strongest published attack testing is at least this. Definitions

Keep hidden from the verifier

What must the verifier never see? Choose any.

Model weights: the checked model's parameters. Inputs and outputs: the requests a deployed model serves and its responses. Training data: what a model was trained on. Each mechanism's exposure is the editors' reading of its record: shown, depends on the design (kept, with a note), hidden, not involved, or unspecified for a selected implementation. Code and configuration are not covered yet.

Removes mechanisms that show the asset to the verifier. Conditional or unspecified exposure stays with a note and needs checking against the privacy requirement.

Claims

A claim is something one party wants to verify about another party's AI hardware or software. Each claim's number shows how the proposal addresses it.

  • Addressed. A mechanism in the proposal is aimed at this claim and is not excluded by the filters.
  • Partly addressed. Only supporting mechanisms, or mechanisms aimed at it that the filters exclude.
  • Unaddressed. No mechanism in the proposal addresses this claim.

Addressed means a mechanism in the proposal is aimed at the claim and is not excluded by your filters. It does not mean the claim is verified: check its assessed use, readiness, assumptions and open flaws.

All claims

Mechanisms

A mechanism is a general technique for verifying claims. Its badge is its readiness level for its stated use. An optional implementation choice narrows its assumptions, assessed use and claim links to that record. Lines join it to the claims it addresses. Click a line for details.Under its name it lists the claims it is aimed at or supports.

  • Aimed at the claim: verifying it is a direct purpose of the mechanism.
  • Supports the claim: helps verify it without being aimed at it.
  • Faint: excluded by your filters, so it does not count towards claim coverage.

All mechanisms

Overview

One row per mechanism in the proposal. Every mark comes from that mechanism's record, as listed in the panels below; what the verifier sees is the editors' reading of the record's text. Flaw counts are per mechanism. Summary counts name mechanisms with open findings, not a sum of attacks. Choosing an implementation narrows each row to that record's assessed use; family findings remain as context.

What the verifier sees

For model weights, inputs and outputs, and training data. This is the editors' reading of each mechanism's record (its threat model, how it works and its limitations), not a field of the record. Shown: the verifier sees it. Depends: on the design or variant, or the verifier sees only samples. Hidden: the verifier sees only commitments, hashes, proofs or results. Not involved: the record does not handle it. Unspecified: the selected implementation has no asset-specific assessment here.

Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open flaw or a dependency. They are pointers, not recommendations: each brings its own readiness level and flaws, and none is claimed to close a flaw. Links from flaws are the editors' reading of the two records.

Start from a published design

Choosing a design loads the mechanisms its record realises or depends on. If the proposal has no claims yet, it also loads the claims that record says the design addresses.

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