Proposal Explorer

Add claims to see which ones the mechanisms address.

In production

• R3 Sampled inference recomputation for checking untrusted workers' activations against the declared model, prompt and precision

Built for an adversarial prover

Chip location verification, Bandwidth limits and compartmentalization, Tamper evidence for verifier devices and Sampled inference recomputation

No new hardware needed

Chip location verification and Sampled inference recomputation

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Chip location verification: Analysis
• Bandwidth limits and compartmentalization: Analysis
• Tamper evidence for verifier devices: Analysis
• Sampled inference recomputation: Analysis

Open significant flaws

15 flaws in 4 mechanisms

• Extracting a chip's key lets another device answer for it in Chip location verification

  Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM. ^{1 6}

  Theoretical argument · Significant · Open. On the record

• Added delay can shift an estimated position in Chip location verification

  Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location. ^{1 4}

  Demonstrated attack · Significant · Open. On the record

• Faster-than-assumed network paths in Chip location verification

  Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often. ^{1 4}

  Theoretical argument · Significant · Open. On the record

• Compromised landmarks can falsify measurements in Chip location verification

  A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators. ^{1 4 5}

  Theoretical argument · Significant · Open. On the record

• Low-communication training reduces the bandwidth training needs in Bandwidth limits and compartmentalization

  DiLoCo matched fully synchronous training on 8 workers while communicating 500 times less. Rahman writes that this family of methods theoretically allows large-scale training with less than 100 Mbps. Lucid includes these methods in its bounds, but notes that extreme activation compression, architectures with unusually small inter-layer widths, or modular paradigms could erode the margin. ^{9 13 14}

  Theoretical argument · Significant · Open. On the record

• Operator control of pod routing collapses the bound in Bandwidth limits and compartmentalization

  Lucid's analysis finds that if the operator can freely assign pods to routers, it could dedicate a whole cell of 100 or more pods to one pipeline stage. The bound then falls to about 90–220x uncompressed and as low as about 25x with compression. The proposed mitigation, auditor-controlled random assignment that is periodically re-randomized, has not been implemented. ⁹

  Theoretical argument · Significant · Open. On the record

• Undeclared local storage raises per-pod capacity in Bandwidth limits and compartmentalization

  More memory or storage per pod helps an adversary. Lucid requires per-pod storage to be declared, capped and physically inspected. ⁹

  Theoretical argument · Significant · Open. On the record

• Training within one pod is not covered in Bandwidth limits and compartmentalization

  Lucid's bounds concern pre-training models larger than the pods are sized for. Training models that fit in one pod, fine-tuning and reinforcement-learning post-training within one pod are outside the modelled threat. ⁹

  Open question · Significant · Open. On the record

• Parallel scale-up switches are hard enforcement points in Bandwidth limits and compartmentalization

  In GB200 topologies, GPUs reach GPUs in other nodes through NVSwitches without a NIC on the path. Amodo notes that limits are hard to enforce there because many switches work in parallel, so compromising one or two would bypass the limit. ¹²

  Theoretical argument · Significant · Open. On the record

• Seals are often defeated with simple methods in Tamper evidence for verifier devices

  Published defeats of general security seals. They warn about proposed verifier-device seals, but do not demonstrate defeat of an AI verification enclosure or sensor.

  In 1996 a Los Alamos vulnerability assessment defeated all 94 security seals it examined, with 132 defeats in total, using rapid, inexpensive, low-tech methods. It found that seal cost did not predict security. In 2001 Johnston reported that high-tech seals are often easier to defeat than low-tech ones. ^{21 22}

  Demonstrated attack · Significant · Open · Mechanism-class evidence. On the record

• Security depends on inspection protocols in Tamper evidence for verifier devices

  An inspection and protocol requirement drawn from safeguards and enclosure studies, not a reported break of a deployed AI verifier.

  Johnston argues that a seal is no better than the protocols for using it, and that inspectors are usually given little useful information on how to detect tampering. The Sandia survey notes that larger enclosures are hard to inspect fully and that sensor data must be authenticated. ^{20 22}

  Theoretical argument · Significant · Open · Mechanism-class evidence. On the record

• Attack classes outside published models in Tamper evidence for verifier devices

  The radio compensation result is emulated using measured channel data under a known-reference attacker model. It is not a physical bypass demonstration against an AI verifier enclosure.

  The authors of the batteryless cover say they cannot assess chemical-solvent attacks, which exceed their expertise, and deem cover removal impractical. Anti-Tamper Radio's reference can drift as the environment or measurement system ages; the authors suggest gradually renewing the reference. A 2025 follow-up by some of the same authors shows, by emulation on measured channel data, that an attacker who knows the reference channel and the needle's effect on it could inject a signal that cancels the change caused by a needle insertion. It proposes a reconfigurable intelligent surface that randomizes the channel as a countermeasure. ^{15 16 23}

  Open question · Significant · Open · Mechanism-class evidence. On the record

• Tolerance for numerical noise leaves a covert channel in Sampled inference recomputation

  Schemes that accept approximate matches can put an upper bound on an adversary's covert bandwidth, but they cannot close the channel. The weight-exfiltration detector cut exfiltratable information to under 0.5%, not to zero, on a 30-billion-parameter mixture-of-experts model under benign prompt traffic. Its authors called the channel's size under adversarial prompts an open empirical question. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token. Across six models, that cut the slowdown from 146–254 times under benign prompts to 60–118 times. The attack widens the exfiltration bound. It does not target the check that outputs match the declared model. ^{24 32 35}

  Demonstrated attack · Significant · Open. On the record

  Related mechanism R3 Deterministic and bit-exact inference: Bit-exact inference would remove the numerical tolerance if exact replay can be deployed with the required weights and configuration. A pointer, not evidence that this flaw is mitigated. Add

• Only recorded traffic is checked in Sampled inference recomputation

  Recomputation checks that recorded, declared workloads are correct. It cannot show that the record is complete. The published schemes do not cover hidden workloads run on the same compute, or substituted work. Rinberg et al. say their exfiltration-detection scheme cannot stand alone. ^{24 36}

  Theoretical argument · Significant · Open. On the record

  Related mechanism R1 Network taps and certifiers: Taps copy and hash all traffic on the monitored links, which bears on whether the traffic record is complete. They do not show what else ran on the same chips. A pointer, not evidence that this flaw is mitigated. Add

• Some inference optimizations are not covered in Sampled inference recomputation

  TOPLOC's authors state that it cannot detect speculative decoding in which a cheaper model does the decoding. They did not test whether it distinguishes types of key-value (KV) cache compression. DiFR was evaluated only on sampling from a single model. Its authors sketch an extension to one speculative-decoding algorithm but do not test it. ^{25 26}

  Theoretical argument · Significant · Open. On the record

Open minor flaws

1 mechanism with minor findings

• Mixed hardware widens the honest baseline in Sampled inference recomputation

  When honest reference runs span different GPU types, the spread of benign scores grows. In DiFR's tests on Qwen3-30B-A3B, pooling A100 and H200 runs left Token-DiFR unable to separate the two smallest tested changes, a temperature of 1.1 instead of 1.0 and a simulated top-2 sampling bug, at the target false-positive rate, while cross-entropy separated them. Matched provider and verifier environments, or pooling that weights rare large deviations, restored detection. ²⁵

  Open question · Minor · Open. On the record

Not yet demonstrated

R1 Chip location verification

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R3 Deterministic and bit-exact inference Add
  • Bears on the open significant flaw “Tolerance for numerical noise leaves a covert channel” in Sampled inference recomputation. Bit-exact inference would remove the numerical tolerance if exact replay can be deployed with the required weights and configuration.
• R1 Network taps and certifiers Add
  • Bears on the open significant flaw “Only recorded traffic is checked” in Sampled inference recomputation. Taps copy and hash all traffic on the monitored links, which bears on whether the traffic record is complete. They do not show what else ran on the same chips.
  • Bandwidth limits and compartmentalization waits on it. The verifier must know that all traffic leaving a pod crosses the capped, monitored links.
  • Sampled inference recomputation waits on it. In tap-based retrofit designs, recording all inference traffic needs network taps and recomputation servers that can ingest it, in the worst case one recomputation-server network interface per inference front-end interface.
• R3 TEE remote attestation for AI workloads Add
  • Chip location verification depends on it.

Missing prerequisites

• R3 TEE remote attestation for AI workloads needed by Chip location verification Add

Shared foundations

• Network taps and certifiers relied on by Bandwidth limits and compartmentalization and Sampled inference recomputation

Blockers

17 blockers recorded

• Chip location verification
  • No public code or reproducible end-to-end location results are available for the reported H100 prototype. Adversarial validation ^{2 3}
  • Per-chip keys must be provisioned and protected against extraction; hardware-integrated, tamper-resistant versions still need R&D. Hardware trust ^{1 6 37}
  • The time limit forces a trade-off: a limit at the speed of light in fibre can be beaten by faster links, while one at the vacuum speed of light makes honest chips fail often. Protocol soundness ¹
  • A trusted landmark network must be built and secured, and who should operate it, under what oversight, is unsettled. Access & governance ^{1 4}
• Bandwidth limits and compartmentalization
  • No cap that a verifier can check has been implemented or red-teamed. Adversarial validation ⁹
  • The verifier must know that all traffic leaving a pod crosses the capped, monitored links. Coverage & hidden compute. Waits on Network taps and certifiers ¹⁰
  • Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU. Hardware trust. Waits on Tamper evidence for verifier devices ^{9 12}
  • Advances in low-communication training could shrink the margin that the cap enforces. Capacity bounds ^{9 13 14}
• Tamper evidence for verifier devices
  • No tamper-evident enclosure has been designed for AI verifier hardware at retrofit scale. Hardware trust ¹⁰
  • Battery-backed designs add bulk, limit operating temperature (+10 °C to +35 °C for the IBM 4765) and complicate transport. Performance & compatibility ¹⁶
  • Active monitoring needs power, and visual inspection of large enclosures faces access limits. Access & governance ²⁰
  • No evaluation has been published in the AI verification setting. Adversarial validation ¹⁰
• Sampled inference recomputation
  • In tap-based retrofit designs, recording all inference traffic needs network taps and recomputation servers that can ingest it, in the worst case one recomputation-server network interface per inference front-end interface. Coverage & hidden compute. Waits on Network taps and certifiers ^{8 31}
  • In retrofit designs, the recomputation server must sit inside the prover's data centre, possibly under the prover's physical control, and still be protected from a compromised provider, which Amodo rates 'not on track'. Hardware trust ^{24 31}
  • No independent red-team of a recomputation consistency check has been published (the one independent attack study targets the weight-exfiltration bound), and Amodo rates recomputation red-teaming 'not started'. Adversarial validation ^{31 32}
  • Tolerance-based checks need calibration on trusted hardware and exact knowledge of the provider's sampling procedure, and in one prototype a sampling-implementation mismatch produced large spurious differences. Performance & compatibility ^{25 30}
  • The verifier needs the model weights, so checking a closed-weights model requires a trusted, confidential recomputation environment, which the retrofit designs place inside the prover's facility. Privacy & leakage ^{10 25 36}

From the family or selected implementation's record. ?

Model weights

Depends on the design for Sampled inference recomputation.

Not involved: Chip location verification, Bandwidth limits and compartmentalization and Tamper evidence for verifier devices.

Inputs and outputs

Depends on the design for Sampled inference recomputation.

Not involved: Chip location verification, Bandwidth limits and compartmentalization and Tamper evidence for verifier devices.

Training data

Not involved: Chip location verification, Bandwidth limits and compartmentalization, Tamper evidence for verifier devices and Sampled inference recomputation.

Chip location verification

• R1 Lucid sovereignty (location) certificates Standard, Lucid Computing

Bandwidth limits and compartmentalization

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 RAND secure inference data center (SIDC) design Proposed architecture, RAND

Tamper evidence for verifier devices

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project

Sampled inference recomputation

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R2 DiFR (Divergence From Reference) Research prototype
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• R1 SASH confidential network logger Research prototype, Singapore AI Safety Hub (SASH)
• R3 TOPLOC Open-source project, Prime Intellect

1. Location Verification for AI Chips, A. Brass & O. Aarne (2024). Original
2. Location Verification for AI Chips (issue brief), A. Brass (2025). Original
3. Ping-based Location, Ulyssean (2025). Original
4. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
5. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). Original
6. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). Original
7. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
8. Verification Plan, R. Dean (2026). Original
9. Traffic Shaping for Workload Classification, Lucid Computing (2026). Original
10. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
11. De-risking Interconnect Limits for AI Verification, A. Scher et al. (2026). Original
12. The Tray as a Bandwidth Boundary, Amodo Design (2026). Original
13. DiLoCo: Distributed Low-Communication Training of Language Models, A. Douillard et al. (2024). Original
14. Does Distributed Training Undermine Compute Governance?, R. Rahman (2026). Original
15. Anti-Tamper Radio: System-Level Tamper Detection for Computing Systems, P. Staat et al. (2022). Original
16. Secure Physical Enclosures from Covers with Tamper-Resistance, V. Immler et al. (2019). Original
17. ImpedanceVerif: On-Chip Impedance Sensing for System-Level Tampering Detection, T. Mosavirik et al. (2023). Original
18. IBM 4765 Cryptographic Coprocessor Security Module: Security Policy, IBM Corporation (2012). Original
19. PHYSEC SEAL: Change detection for maximum safety, PHYSEC GmbH (2026). Original
20. Tamper-Indicating Enclosures, A Current Survey, H. A. Smartt & Z. N. Gastelum (2015). Original
21. Physical Security and Tamper-Indicating Devices, R. G. Johnston & A. R. E. Garcia (1996). Original
22. Tamper Detection for Safeguards and Treaty Monitoring: Fantasies, Realities, and Potentials, R. G. Johnston (2001). Original
23. Anti-Tamper Radio Meets Reconfigurable Intelligent Surface for System-Level Tamper Detection, M. S. Tabar et al. (2025). Original
24. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
25. DiFR: Inference Verification Despite Nondeterminism, A. Karvonen et al. (2025). Original
26. TOPLOC: A Locality Sensitive Hashing Scheme for Trustless Verifiable Inference, J. M. Ong et al. (2025). Original
27. PrimeIntellect-ai/toploc (GitHub repository), Prime Intellect (2025). Original
28. INTELLECT-2: A Reasoning Model Trained Through Globally Decentralized Reinforcement Learning, Prime Intellect Team et al. (2025). Original
29. adamkarvonen/difr (GitHub repository), A. Karvonen (2025). Original
30. Scaling Recomputation Inference Verification, Amodo Design (2026). Original
31. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original
32. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
33. SYNTHETIC-2 Release: Four Million Collaboratively Generated Reasoning Traces, Prime Intellect (2025). Original
34. An Inference Verification Prototype — Stage 1, Amodo Design (2026). Original
35. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
36. Example Schemes for Verifying High-Stakes AI Agreements, Amodo Design (2026). Original
37. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original