Proposal Explorer

Add claims to see which ones the mechanisms address.

In production

• R3 Model identity attestation for showing users that a service runs the declared model weights

Built for an adversarial prover

Side-channel suppression for isolated facilities and Timed challenge-response and memory-occupation challenges

No new hardware needed

Timed challenge-response and memory-occupation challenges and Model identity attestation

Flaws since mitigated

• Launch-state attestation does not by itself cover weights loaded later in Model identity attestation ^{12 24}

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Side-channel suppression for isolated facilities: Analysis
• Timed challenge-response and memory-occupation challenges: Analysis
• Model identity attestation: Independent red-team

Open critical flaws

• Underlying attestation can be forged or relayed in Model identity attestation

  Critical for the enclave route against an operator with physical access to affected hardware, or control of an unpatched SEV-SNP hypervisor. It does not apply to the recomputation route. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary.

  The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. ^{13 15 19 21 22 23}

  Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

  Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

  Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this flaw is mitigated. Add

Open significant flaws

6 flaws in 3 mechanisms

• Supply-chain implants may evade inspection in Side-channel suppression for isolated facilities

  Cankaya identifies malicious hardware embedded deep in purchased components as a residual risk that visual inspection and disassembly may not catch. He notes that radiographic examination under high-security standards could mitigate it. ¹

  Theoretical argument · Significant · Open. On the record

• Openings for airflow, power and optics weaken shielding in Side-channel suppression for isolated facilities

  Cankaya notes that keeping attenuation high while passing high-power airflow, cabling and optical links adds complexity beyond existing shielded-enclosure specifications. ¹

  Theoretical argument · Significant · Open. On the record

• Inspection assumptions may not hold in Side-channel suppression for isolated facilities

  The design's statistical argument assumes that visual or disassembly inspection catches every flaw that is present in a sampled unit. Cankaya is unsure whether destructive teardowns are defence-dominant or offence-dominant. ¹

  Open question · Significant · Open. On the record

• Remote memory narrows the timing margin in Timed challenge-response and memory-occupation challenges

  Data-centre remote memory access returns in about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview says verification of memory saturation depends on ruling out remote access by latency or physical disconnection. It adds that pre-staging data is ruled out only by unpredictable, capacity-filling challenges. ²

  Theoretical argument · Significant · Open. On the record

  Related mechanism R2 Bandwidth limits and compartmentalization: Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced. A pointer, not evidence that this flaw is mitigated. Add

• For private models, a user can confirm consistency but not content in Model identity attestation

  When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy. ^{12 25}

  Open question · Significant · Open. On the record

• Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel in Model identity attestation

  The recomputation variant assumes that every input, output and seed is logged correctly, and that the attacker can neither predict nor manipulate which messages are sampled for verification. Legitimate nondeterminism concentrates at a few token positions, and slow leaks within the tolerated slack remain possible. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token, reducing the exfiltration slowdown from 146–254 times under benign prompts to 60–118 times. The attack targets the exfiltration bound, not the check that outputs match the declared model. ^{14 20}

  Demonstrated attack · Significant · Open. On the record

  Related mechanism R1 Network taps and certifiers: Taps are proposed to copy and hash traffic on the monitored links, reducing reliance on the prover's own log. This still depends on the monitored boundary and trusted capture. A pointer, not evidence that this flaw is mitigated. Add

  Related mechanism R3 Deterministic and bit-exact inference: Bit-exact inference would remove the numerical tolerance that leaves this channel. A pointer, not evidence that this flaw is mitigated. Add

Open minor flaws

1 mechanism with minor findings

• Error rates not quantified in Timed challenge-response and memory-occupation challenges

  Monfared et al. show separable timing distributions but do not define thresholds or statistical tests, so false-positive and false-negative rates are not quantified. ⁴

  Open question · Minor · Open. On the record

Not yet demonstrated

R1 Side-channel suppression for isolated facilities

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R1 Hardware-enabled guarantees (flexHEG) and guarantee processors Add
  • Bears on the open critical flaw “Underlying attestation can be forged or relayed” in Model identity attestation. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
• R3 Deterministic and bit-exact inference Add
  • Bears on the open significant flaw “Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel” in Model identity attestation. Bit-exact inference would remove the numerical tolerance that leaves this channel.
  • Model identity attestation waits on it. Numerical nondeterminism limits how tightly recomputation can pin down the model and sampling.
• R2 Bandwidth limits and compartmentalization Add
  • Bears on the open significant flaw “Remote memory narrows the timing margin” in Timed challenge-response and memory-occupation challenges. Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced.
  • Timed challenge-response and memory-occupation challenges waits on it. Outside help, such as remote memory, must be excluded during challenges.
• R1 Network taps and certifiers Add
  • Bears on the open significant flaw “Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel” in Model identity attestation. Taps are proposed to copy and hash traffic on the monitored links, reducing reliance on the prover's own log. This still depends on the monitored boundary and trusted capture.
• R3 TEE remote attestation for AI workloads Add
  • Model identity attestation waits on it. Attestation that resists physical attackers, for the enclave variant.

Blockers

8 blockers recorded

• Side-channel suppression for isolated facilities
  • No prototype or red-team exists; the design is a first-pass viability study. Adversarial validation ¹
  • Volume costs of TEMPEST-grade power-line filters are uncertain, because existing products are mostly made to order. Performance & compatibility ¹
• Timed challenge-response and memory-occupation challenges
  • No network-level memory challenge across data-centre servers has been demonstrated. Adversarial validation ²
  • Challenges that fill memory displace workloads; filling a pod's volatile memory takes tens of minutes and SSDs take hours. Performance & compatibility ^{2 4}
  • Outside help, such as remote memory, must be excluded during challenges. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization ²
• Model identity attestation
  • Attestation that resists physical attackers, for the enclave variant. Hardware trust. Waits on TEE remote attestation for AI workloads ¹⁹
  • Numerical nondeterminism limits how tightly recomputation can pin down the model and sampling. Protocol soundness. Waits on Deterministic and bit-exact inference ¹⁴
  • The recomputation variant needs the verifier to hold the declared weights. Access & governance ¹⁴

From the family or selected implementation's record. ?

Model weights

Depends on the design for Model identity attestation.

Not involved: Side-channel suppression for isolated facilities and Timed challenge-response and memory-occupation challenges.

Inputs and outputs

Depends on the design for Model identity attestation.

Not involved: Side-channel suppression for isolated facilities and Timed challenge-response and memory-occupation challenges.

Training data

Not involved: Side-channel suppression for isolated facilities, Timed challenge-response and memory-occupation challenges and Model identity attestation.

Side-channel suppression for isolated facilities

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• R1 RAND secure inference data center (SIDC) design Proposed architecture, RAND

Timed challenge-response and memory-occupation challenges

• R1 Data-centre memory challenging Proposed architecture, Machine Intelligence Research Institute
• R2 GPU contention probes Research prototype
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• R2 SAGE Research prototype
• R2 VRAM-residency challenge Research prototype

Model identity attestation

• R2 Attestable Audits Research prototype, University of Cambridge
• R2 PAL*M Research prototype, University of Waterloo
• R3 Tinfoil model identity (Modelwrap) Product, Tinfoil

1. Suppressing Side Channels in an Untrusted Data Center via Retrofitted Defenses, N. Cankaya (2026). Original
2. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
3. Verification Plan, R. Dean (2026). Original
4. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
5. SAGE: Software-based Attestation for GPU Execution, A. Ivanov et al. (2023). Original
6. SWATT: SoftWare-based ATTestation for Embedded Devices, A. Seshadri et al. (2004). Original
7. Proofs of Space, S. Dziembowski et al. (2015). Original
8. Secure Code Update for Embedded Devices via Proofs of Secure Erasure, D. Perito & G. Tsudik (2010). Original
9. Software-Based Memory Erasure with Relaxed Isolation Requirements, S. Bursuc et al. (2024). Original
10. On the Difficulty of Software-Based Attestation of Embedded Devices, C. Castelluccia et al. (2009). Original
11. Refutation of "On the Difficulty of Software-Based Attestation of Embedded Devices", A. Perrig & L. van Doorn (2010). Original
12. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
13. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
14. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
15. A primer on secure enclaves, Tinfoil (2026). Original
16. Backend infrastructure, Tinfoil (2026). Original
17. How verification works in Tinfoil, Tinfoil (2026). Original
18. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). Original
19. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
20. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
21. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
22. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
23. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
24. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
25. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original