Proposal Explorer

Add claims to see which ones the mechanisms address.

Built for an adversarial prover

Tamper evidence for verifier devices

No new hardware needed

Chip registries and manufacturing records

Not counted

Excluded by your filters: Whole-workload recomputation (reproducible packets)

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Chip registries and manufacturing records: Analysis
• Tamper evidence for verifier devices: Analysis

Excluded by your filters

• Whole-workload recomputation (reproducible packets) Attack testing is none; the filter asks for at least published analysis.

Open significant failures

3 failures in 2 mechanisms

• Documents and serial numbers can be forged in Chip registries and manufacturing records

  Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. ⁸

  Known failure · Theoretical argument · Significant · Open. On the record

• Seals are often defeated with simple methods in Tamper evidence for verifier devices

  Published defeats of general security seals. They warn about proposed verifier-device seals, but do not demonstrate defeat of an AI verification enclosure or sensor.

  In 1996 a Los Alamos vulnerability assessment defeated all 94 security seals it examined, with 132 defeats in total, using rapid, inexpensive, low-tech methods. It found that seal cost did not predict security. In 2001 Johnston reported that high-tech seals are often easier to defeat than low-tech ones. ^{19 20}

  Known failure · Demonstrated attack · Significant · Open · Mechanism-class evidence. On the record

• Attack classes outside published models in Tamper evidence for verifier devices

  The radio compensation result is emulated using measured channel data under a known-reference attacker model. It is not a physical bypass demonstration against an AI verifier enclosure.

  The authors of the batteryless cover say they cannot assess chemical-solvent attacks, which exceed their expertise, and deem cover removal impractical. Anti-Tamper Radio's reference can drift as the environment or measurement system ages; the authors suggest gradually renewing the reference. A 2025 follow-up by some of the same authors shows, by emulation on measured channel data, that an attacker who knows the reference channel and the needle's effect on it could inject a signal that cancels the change caused by a needle insertion. It proposes a reconfigurable intelligent surface that randomizes the channel as a countermeasure. ^{12 13 21}

  Known failure · Open question · Significant · Open · Mechanism-class evidence. On the record

Scope limitations

• Spare compute is outside the scheme in Whole-workload recomputation (reproducible packets)

  The plan states that it does not verify that spare compute is not used for unapproved workloads, because this seems very challenging. Recomputation checks the correctness of declared work, not its completeness. ^{1 2}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Proofs of useful work for capacity accounting: Proposed as one input to accounting for spare capacity on declared hardware. A pointer, not evidence that this failure is mitigated. Add

• Records cover only chips that were recorded in Chip registries and manufacturing records

  A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. ^{9 11}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this failure is mitigated. Add

• Insiders could alter records before they are fixed in Chip registries and manufacturing records

  Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. ⁹

  Scope limitation · Theoretical argument. On the record

• Security depends on inspection protocols in Tamper evidence for verifier devices

  An inspection and protocol requirement drawn from safeguards and enclosure studies, not a reported break of a deployed AI verifier.

  Johnston argues that a seal is no better than the protocols for using it, and that inspectors are usually given little useful information on how to detect tampering. The Sandia survey notes that larger enclosures are hard to inspect fully and that sensor data must be authenticated. ^{17 20}

  Scope limitation · Theoretical argument · Mechanism-class evidence. On the record

Open questions

• Non-compliant work could be encoded inside compliant-looking packets in Whole-workload recomputation (reproducible packets)

  The plan notes that an AI company might try to encode a non-compliant workload inside a workload that looks compliant on the surface. ¹

  Open question · Theoretical argument. On the record

Not yet demonstrated

Proposed Whole-workload recomputation (reproducible packets) and Proposed Chip registries and manufacturing records

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Operational use Deterministic and bit-exact inference Add
  • Whole-workload recomputation (reproducible packets) waits on it. Workloads are not reproducible by default, and achieving reproducibility may cost performance.
• Proposed Network taps and certifiers Add
  • Whole-workload recomputation (reproducible packets) waits on it. All traffic must reach the recomputation server via network taps, and the server's integrity is critical.

Missing prerequisites

• Operational use Deterministic and bit-exact inference needed by Whole-workload recomputation (reproducible packets) Add
• Proposed Network taps and certifiers needed by Whole-workload recomputation (reproducible packets) Add

Blockers

11 blockers recorded

• Whole-workload recomputation (reproducible packets)
  • Workloads are not reproducible by default, and achieving reproducibility may cost performance. Performance & compatibility. Waits on Deterministic and bit-exact inference ¹
  • Network packets are not individually reproducible by default; making them so may need considerable software, firmware and hardware work. Amodo rates this 'not on track'. Performance & compatibility ⁴
  • All traffic must reach the recomputation server via network taps, and the server's integrity is critical. Hardware trust. Waits on Network taps and certifiers ^{1 4}
  • Recomputing training steps needs checkpoints: writing one at every step would cost more than 100% overhead, so Amodo's design needs a spare data-parallel replica that tracks the weights instead. Performance & compatibility ²
• Chip registries and manufacturing records
  • No implementation of an AI chip registry has been publicly reported, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance ^{7 8}
  • Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust ^{7 8 9}
  • Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute ^{9 11}
• Tamper evidence for verifier devices
  • No tamper-evident enclosure has been designed for AI verifier hardware at retrofit scale. Hardware trust ¹⁸
  • Battery-backed designs add bulk, limit operating temperature (+10 °C to +35 °C for the IBM 4765) and complicate transport. Performance & compatibility ¹³
  • Active monitoring needs power, and visual inspection of large enclosures faces access limits. Access & governance ¹⁷
  • No evaluation has been published in the AI verification setting. Adversarial validation ¹⁸

From the family or selected implementation's record. ?

Model weights

Depends on the design for Whole-workload recomputation (reproducible packets).

Not involved: Chip registries and manufacturing records and Tamper evidence for verifier devices.

Inputs and outputs

Depends on the design for Whole-workload recomputation (reproducible packets).

Not involved: Chip registries and manufacturing records and Tamper evidence for verifier devices.

Training data

Depends on the design for Whole-workload recomputation (reproducible packets).

Not involved: Chip registries and manufacturing records and Tamper evidence for verifier devices.

Whole-workload recomputation (reproducible packets)

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project

Chip registries and manufacturing records

None on the map

Tamper evidence for verifier devices

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project

1. Verification Plan, R. Dean (2026). Original
2. Example Schemes for Verifying High-Stakes AI Agreements, Amodo Design (2026). Original
3. Scaling Recomputation Inference Verification, Amodo Design (2026). Original
4. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original
5. Get Involved in Verification, AI Futures Project (2026). Original
6. Proof-of-Learning is Currently More Broken Than You Think, C. Fang et al. (2023). Original
7. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
8. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
9. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
10. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
11. Covert AI Projects, B. Halstead & T. Larsen (2026). Original
12. Anti-Tamper Radio: System-Level Tamper Detection for Computing Systems, P. Staat et al. (2022). Original
13. Secure Physical Enclosures from Covers with Tamper-Resistance, V. Immler et al. (2019). Original
14. ImpedanceVerif: On-Chip Impedance Sensing for System-Level Tampering Detection, T. Mosavirik et al. (2023). Original
15. IBM 4765 Cryptographic Coprocessor Security Module: Security Policy, IBM Corporation (2012). Original
16. PHYSEC SEAL: Change detection for maximum safety, PHYSEC GmbH (2026). Original
17. Tamper-Indicating Enclosures, A Current Survey, H. A. Smartt & Z. N. Gastelum (2015). Original
18. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
19. Physical Security and Tamper-Indicating Devices, R. G. Johnston & A. R. E. Garcia (1996). Original
20. Tamper Detection for Safeguards and Treaty Monitoring: Fantasies, Realities, and Potentials, R. G. Johnston (2001). Original
21. Anti-Tamper Radio Meets Reconfigurable Intelligent Surface for System-Level Tamper Detection, M. S. Tabar et al. (2025). Original