Proposal Explorer

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Operational use

• Operational use Hardware-attested weight binding for hardware-attested weight binding showing users that a service runs its committed weights

Built for an adversarial prover

Remote detection of data centres

No new hardware needed

On-chip telemetry from timing, memory and performance counters, Remote detection of data centres, Hardware-attested weight binding and Chip registries and manufacturing records

Failures since mitigated

• Launch-state attestation does not by itself cover weights loaded later in Hardware-attested weight binding ^{4 11}

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• On-chip telemetry from timing, memory and performance counters: Red-teamed
• Remote detection of data centres: Analysis
• Hardware-attested weight binding: Independent red-team
• Chip registries and manufacturing records: Analysis

Open critical failures

• Underlying attestation can be forged or relayed in Hardware-attested weight binding

  Critical for weight binding against an operator with physical access to affected hardware, or with control of the hypervisor on an AMD SEV-SNP platform without AMD's fixes. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary.

  The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. ^{12 13 17 18 19 20}

  Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

  Known failure · Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this failure is mitigated. Add

Open significant failures

3 failures in 2 mechanisms

• Adversarially disguised fine-tuning partly evades classification in On-chip telemetry from timing, memory and performance counters

  Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware. ³

  Known failure · Demonstrated attack · Significant · Open. On the record

• Counters leak information about protected workloads in On-chip telemetry from timing, memory and performance counters

  Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality. ^{4 5}

  Known failure · Theoretical argument · Significant · Open. On the record

• Documents and serial numbers can be forged in Chip registries and manufacturing records

  Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. ²²

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Software-read telemetry can be forged by the operator in On-chip telemetry from timing, memory and performance counters

  NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized. ^{1 3}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing. A pointer, not evidence that this failure is mitigated. Add

• Timing challenges do not identify the individual chip in On-chip telemetry from timing, memory and performance counters

  GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use. ¹

  Scope limitation · Theoretical argument. On the record

• Facilities can be disguised or hidden in Remote detection of data centres

  Halstead and Larsen discuss two ways to hide a facility. One is to disguise it as a legitimate industrial site. The other is to build it underground, with cooling that avoids visible heat plumes. They note that the underground option requires bespoke engineering. ⁶

  Scope limitation · Theoretical argument. On the record

• Small sites may not be detectable in Remote detection of data centres

  Halstead and Larsen conclude that a sufficiently small covert project could not be ruled out with confidence. In their estimates, the chance of detection is lower for smaller sites. Krawec notes that small data centres in existing buildings may lack the distinctive features of large facilities. ^{6 8}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Chip registries and manufacturing records: Accounts for chips from the fab onwards, which does not depend on a site being visible. A pointer, not evidence that this failure is mitigated. In the proposal.

• For private models, a user can confirm consistency but not content in Hardware-attested weight binding

  When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy. ^{11 21}

  Scope limitation · Open question. On the record

• Records cover only chips that were recorded in Chip registries and manufacturing records

  A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. ^{6 23}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this failure is mitigated. In the proposal.

• Insiders could alter records before they are fixed in Chip registries and manufacturing records

  Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. ²³

  Scope limitation · Theoretical argument. On the record

Open questions

• No quantified error rates or formal thresholds for timing primitives in On-chip telemetry from timing, memory and performance counters

  Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work. ¹

  Open question · Open question. On the record

• Search for unknown sites is undemonstrated in Remote detection of data centres

  Krawec reports that telling data centres apart from other industrial facilities systematically is difficult. Automating detection would need large amounts of training imagery and a purpose-trained model. In Krawec's words, automated data-centre detection "remains primarily conceptual at present". ⁸

  Open question · Open question. On the record

Not yet demonstrated

Proposed Remote detection of data centres and Proposed Chip registries and manufacturing records

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Operational use TEE remote attestation for AI workloads Add
  • Hardware-attested weight binding waits on it. Attestation that resists physical attackers, for the enclave variant.
  • On-chip telemetry from timing, memory and performance counters depends on it.
• Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors Add

  Excluded by filters: needs new chips

  • Bears on the open critical failure “Underlying attestation can be forged or relayed” in Hardware-attested weight binding. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
  • On-chip telemetry from timing, memory and performance counters waits on it. Shipping accelerators need a tamper-resistant, authenticated telemetry path.

Missing prerequisites

• Operational use TEE remote attestation for AI workloads needed by On-chip telemetry from timing, memory and performance counters and Hardware-attested weight binding Add

Shared foundations

• TEE remote attestation for AI workloads relied on by On-chip telemetry from timing, memory and performance counters and Hardware-attested weight binding

Blockers

11 blockers recorded

• On-chip telemetry from timing, memory and performance counters
  • Shipping accelerators need a tamper-resistant, authenticated telemetry path. Hardware trust. Waits on Hardware-enabled guarantees (flexHEG) and guarantee processors ^{2 3}
  • NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. Privacy & leakage ^{4 5}
  • Continuous challenge puzzles cost power and throughput on production workloads. Performance & compatibility ¹
  • Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. Adversarial validation ³
• Remote detection of data centres
  • Wide-area, automated detection of data centres is not yet practical and needs large training datasets. Coverage & hidden compute ⁸
  • No measured detection or false-alarm rates for finding undeclared facilities have been published. Adversarial validation ^{6 8}
  • Recent high-resolution imagery is costly, is limited by weather and needs trained analysts. Access & governance ⁸
• Hardware-attested weight binding
  • Attestation that resists physical attackers, for the enclave variant. Hardware trust. Waits on TEE remote attestation for AI workloads ¹⁷
• Chip registries and manufacturing records
  • No implementation of an AI chip registry has been publicly reported, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance ^{7 22}
  • Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust ^{7 22 23}
  • Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute ^{6 23}

From the family or selected implementation's record. ?

Model weights

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Hidden by Hardware-attested weight binding.

Not involved: Remote detection of data centres and Chip registries and manufacturing records.

Inputs and outputs

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Remote detection of data centres and Chip registries and manufacturing records.

Unspecified for Hardware-attested weight binding. Check the implementation record.

Training data

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Remote detection of data centres, Hardware-attested weight binding and Chip registries and manufacturing records.

On-chip telemetry from timing, memory and performance counters

None on the map

Remote detection of data centres

None on the map

Hardware-attested weight binding

• Research demo Attestable Audits Research prototype, University of Cambridge
• Research demo PAL*M Research prototype, University of Waterloo
• Operational use Tinfoil model identity (Modelwrap) Product, Tinfoil

Chip registries and manufacturing records

None on the map

1. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
2. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). Original
3. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). Original
4. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
5. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original
6. Covert AI Projects, B. Halstead & T. Larsen (2026). Original
7. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
8. Tracking Hyperscale AI Data Center Growth with Satellite Imagery, C. Krawec (2026). Original
9. Introducing the Frontier Data Centers Hub, Epoch AI (2025). Original
10. AI Data Centers Documentation – Methodology, Epoch AI (2026). Original
11. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
12. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
13. A primer on secure enclaves, Tinfoil (2026). Original
14. Backend infrastructure, Tinfoil (2026). Original
15. How verification works in Tinfoil, Tinfoil (2026). Original
16. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). Original
17. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
18. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
19. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
20. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
21. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original
22. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
23. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
24. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original