Proposal Explorer

Add claims to see which ones the mechanisms address.

Operational use

• Operational use Hardware-attested weight binding for hardware-attested weight binding showing users that a service runs its committed weights

Built for an adversarial prover

Memory wiping and proofs of secure erasure

No new hardware needed

Memory wiping and proofs of secure erasure and Hardware-attested weight binding

Failures since mitigated

• Launch-state attestation does not by itself cover weights loaded later in Hardware-attested weight binding ^{9 19}

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Memory wiping and proofs of secure erasure: Analysis
• Hardware-attested weight binding: Independent red-team

Open critical failures

• Underlying attestation can be forged or relayed in Hardware-attested weight binding

  Critical for weight binding against an operator with physical access to affected hardware, or with control of the hypervisor on an AMD SEV-SNP platform without AMD's fixes. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary.

  The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. ^{10 11 15 16 17 18}

  Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

  Known failure · Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this failure is mitigated. Add

Open significant failures

1 failure in 1 mechanism

• Outside help during challenges in Memory wiping and proofs of secure erasure

  Classic proofs of secure erasure assume the device is isolated during the protocol. Bursuc et al. relax this to a bound on how close a helper can be, enforced by round-trip times. In data centres, remote memory access has round trips of about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview therefore says verification depends on ruling out RDMA by latency or physical disconnection. ^{3 4}

  Known failure · Theoretical argument · Significant · Open. On the record

  Related mechanism Research demo Timed challenge-response and memory-occupation challenges: Timed challenges bound how far away a helper can be by how quickly it must answer. A pointer, not evidence that this failure is mitigated. Add

  Related mechanism Research demo Bandwidth limits and compartmentalization: Removing or capping links between groups of accelerators limits remote memory access during a challenge. A pointer, not evidence that this failure is mitigated. Add

Scope limitations

• Memory the wipe cannot reach in Memory wiping and proofs of secure erasure

  Amodo's inventory of a GB200 system lists many memory stores beyond GPU HBM and host DRAM. It notes that SSD controller DRAM sits on a private bus that host commands cannot read or write, and that its optimized algorithm leaves 25 GiB of HBM unattested. It also asks how switch memory could be wiped. ^{5 6}

  Scope limitation · Open question. On the record

• Gap between erased and total memory in Memory wiping and proofs of secure erasure

  Bursuc et al. note that memory left between the erased region and the device's full memory could hold data, and that their bounds are tighter only against a restricted adversary. ³

  Scope limitation · Theoretical argument. On the record

• For private models, a user can confirm consistency but not content in Hardware-attested weight binding

  When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy. ^{9 20}

  Scope limitation · Open question. On the record

Not yet demonstrated

Proposed Memory wiping and proofs of secure erasure

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors Add
  • Bears on the open critical failure “Underlying attestation can be forged or relayed” in Hardware-attested weight binding. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
• Research demo Bandwidth limits and compartmentalization Add
  • Bears on the open significant failure “Outside help during challenges” in Memory wiping and proofs of secure erasure. Removing or capping links between groups of accelerators limits remote memory access during a challenge.
• Research demo Timed challenge-response and memory-occupation challenges Add
  • Bears on the open significant failure “Outside help during challenges” in Memory wiping and proofs of secure erasure. Timed challenges bound how far away a helper can be by how quickly it must answer.
  • Memory wiping and proofs of secure erasure waits on it. Timed challenges must exclude remote memory and other helpers.
• Operational use TEE remote attestation for AI workloads Add
  • Hardware-attested weight binding waits on it. Attestation that resists physical attackers, for the enclave variant.

Missing prerequisites

• Research demo Timed challenge-response and memory-occupation challenges needed by Memory wiping and proofs of secure erasure Add
• Operational use TEE remote attestation for AI workloads needed by Hardware-attested weight binding Add

Blockers

4 blockers recorded

• Memory wiping and proofs of secure erasure
  • Wipes take time: tens of minutes for a pod's volatile memory and hours for SSDs, displacing work. Performance & compatibility ^{4 5 6}
  • Timed challenges must exclude remote memory and other helpers. Coverage & hidden compute. Waits on Timed challenge-response and memory-occupation challenges ^{3 4}
  • All memory stores in a system must be inventoried and wiped at the same time. Coverage & hidden compute ⁵
• Hardware-attested weight binding
  • Attestation that resists physical attackers, for the enclave variant. Hardware trust. Waits on TEE remote attestation for AI workloads ¹⁵

From the family or selected implementation's record. ?

Model weights

Hidden by Hardware-attested weight binding.

Not involved: Memory wiping and proofs of secure erasure.

Inputs and outputs

Not involved: Memory wiping and proofs of secure erasure.

Unspecified for Hardware-attested weight binding. Check the implementation record.

Training data

Not involved: Memory wiping and proofs of secure erasure and Hardware-attested weight binding.

Memory wiping and proofs of secure erasure

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute

Hardware-attested weight binding

• Research demo Attestable Audits Research prototype, University of Cambridge
• Research demo PAL*M Research prototype, University of Waterloo
• Operational use Tinfoil model identity (Modelwrap) Product, Tinfoil

1. Verification Plan, R. Dean (2026). Original
2. Secure Code Update for Embedded Devices via Proofs of Secure Erasure, D. Perito & G. Tsudik (2010). Original
3. Software-Based Memory Erasure with Relaxed Isolation Requirements, S. Bursuc et al. (2024). Original
4. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
5. Memory Wipes - Performance Analysis, Amodo Design (2026). Original
6. Improving Disk Wiping Speed for Memory Wipes, Amodo Design (2026). Original
7. Amodo-Design/PoSE-Memory-Wiping (GitHub repository), Amodo Design (2026). Original
8. Empirical Evaluation of Memory-Erasure Protocols, R. Gil-Pons et al. (2025). Original
9. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
10. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
11. A primer on secure enclaves, Tinfoil (2026). Original
12. Backend infrastructure, Tinfoil (2026). Original
13. How verification works in Tinfoil, Tinfoil (2026). Original
14. modelwrap: Reproducible dm-verity read-only image of Huggingface models, Tinfoil (2026). Original
15. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
16. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
17. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
18. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
19. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
20. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original