Proposal Explorer

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Excluded by your filters: Chip location verification, Sampled inference recomputation and Deterministic and bit-exact inference

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Chip location verification: Analysis · excluded by filters
• Sampled inference recomputation: Analysis · excluded by filters
• Deterministic and bit-exact inference: Analysis · excluded by filters

Excluded by your filters

• Chip location verification Prover cooperation is required; the filter allows partial at most.
• Sampled inference recomputation Prover cooperation is required; the filter allows partial at most.
• Deterministic and bit-exact inference Prover cooperation is required; the filter allows partial at most.

Open significant failures

6 failures in 2 mechanisms

• Extracting a chip's key lets another device answer for it in Chip location verification

  Ping-based protocols rely on cryptographic keys stored on the chip. Tee and Happel argue that an adversary with physical access could extract these keys and so compromise location verification. They propose GPU fingerprints as a mitigation, so far tested on 24 GPUs. Brass and Aarne assume the keys are stored securely, for example in a TPM. ^{1 6}

  Known failure · Theoretical argument · Significant · Open. On the record

• Added delay can shift an estimated position in Chip location verification

  Brass and Aarne cite internet-geolocation research in which artificially increased round-trip times moved the estimated location by up to 1,000 km, with a 74% chance of avoiding detection. Avellar and Grunewald list inflated ping times from circuitous routing as an evasion route. Added delay only loosens a distance bound, and Brass and Aarne propose a hard time limit as the counter: a chip that replies too slowly cannot be ruled out of a restricted location. ^{1 4}

  Known failure · Demonstrated attack · Significant · Open. On the record

• Faster-than-assumed network paths in Chip location verification

  Brass and Aarne list dark fibre and other private high-speed interconnects as ways to lower measured delays artificially. They judge that leasing dark fibre would probably not be a considerable challenge for covertly or openly adversarial actors. Avellar and Grunewald note that this can make a chip appear to be somewhere else entirely. A limit set at the vacuum speed of light cannot be beaten, but it makes honest chips fail more often. ^{1 4}

  Known failure · Theoretical argument · Significant · Open. On the record

• Compromised landmarks can falsify measurements in Chip location verification

  A party that controls landmark servers can report false timing. Brass and Aarne cite research in which manipulating a third of the landmarks shifted the estimated location by about 700 km. Avellar and Grunewald note that compromised landmarks let adversaries spoof travel-time measurements directly. The draft specification asks verifiers to require anchors in diverse places, run by several independent operators. ^{1 4 5}

  Known failure · Theoretical argument · Significant · Open. On the record

• Tolerance for numerical noise leaves a covert channel in Sampled inference recomputation

  Schemes that accept approximate matches can put an upper bound on an adversary's covert bandwidth, but they cannot close the channel. The weight-exfiltration detector cut exfiltratable information to under 0.5%, not to zero, on a 30-billion-parameter mixture-of-experts model under benign prompt traffic. Its authors called the channel's size under adversarial prompts an open empirical question. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token. Across six models, that cut the slowdown from 146–254 times under benign prompts to 60–118 times. The attack widens the exfiltration bound. It does not target the check that outputs match the declared model. ^{8 16 19}

  Known failure · Demonstrated attack · Significant · Open. On the record

  Related mechanism Operational use Deterministic and bit-exact inference: Bit-exact inference would remove the numerical tolerance if exact replay can be deployed with the required weights and configuration. A pointer, not evidence that this failure is mitigated. In the proposal.

• Some inference optimizations are not covered in Sampled inference recomputation

  TOPLOC's authors state that it cannot detect speculative decoding in which a cheaper model does the decoding. They did not test whether it distinguishes types of key-value (KV) cache compression. DiFR was evaluated only on sampling from a single model. Its authors sketch an extension to one speculative-decoding algorithm but do not test it. ^{9 10}

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Only recorded traffic is checked in Sampled inference recomputation

  Recomputation checks that recorded, declared workloads are correct. It cannot show that the record is complete. The published schemes do not cover hidden workloads run on the same compute, or substituted work. Rinberg et al. say their exfiltration-detection scheme cannot stand alone. ^{8 20}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Network taps and certifiers: Taps copy and hash all traffic on the monitored links, which bears on whether the traffic record is complete. They do not show what else ran on the same chips. A pointer, not evidence that this failure is mitigated. Add

• Some kernels remain genuinely nondeterministic in Deterministic and bit-exact inference

  The bit-exact work separates kernels that are deterministic but not batch-invariant from truly nondeterministic ones that use atomic functions. Some integer de-quantization kernels use atomic additions and remain nondeterministic, so exact replay needs backends that avoid them. ¹⁹

  Scope limitation · Open question. On the record

• Cross-hardware replay relies on reverse-engineered, closed behaviour in Deterministic and bit-exact inference

  Emulating one GPU's rounding on another requires reverse-engineering tensor-core arithmetic and modelling proprietary kernel choices. Hawkeye covers a subset of NVIDIA architectures and states that attention and other higher-level operations need further reverse engineering. For the bit-exact emulator, a proprietary Hopper kernel family is an open edge case. ^{19 23}

  Scope limitation · Open question. On the record

Open minor failures

1 mechanism with minor failures

• Mixed hardware widens the honest baseline in Sampled inference recomputation

  When honest reference runs span different GPU types, the spread of benign scores grows. In DiFR's tests on Qwen3-30B-A3B, pooling A100 and H200 runs left Token-DiFR unable to separate the two smallest tested changes, a temperature of 1.1 instead of 1.0 and a simulated top-2 sampling bug, at the target false-positive rate, while cross-entropy separated them. Matched provider and verifier environments, or pooling that weights rare large deviations, restored detection. ⁹

  Known failure · Open question · Minor · Open. On the record

Not yet demonstrated

Proposed Chip location verification

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Proposed Network taps and certifiers Add

  Excluded by filters: prover cooperation required

  • Sampled inference recomputation waits on it. In tap-based retrofit designs, recording all inference traffic needs network taps and recomputation servers that can ingest it, in the worst case one recomputation-server network interface per inference front-end interface.
• Operational use TEE remote attestation for AI workloads Add

  Excluded by filters: prover cooperation required

  • Chip location verification depends on it.

Missing prerequisites

• Operational use TEE remote attestation for AI workloads needed by Chip location verification Add

Blockers

13 blockers recorded

• Chip location verification
  • No public code or reproducible end-to-end location results are available for the reported H100 prototype. Adversarial validation ^{2 3}
  • Per-chip keys must be provisioned and protected against extraction; hardware-integrated, tamper-resistant versions still need R&D. Hardware trust ^{1 6 31}
  • The time limit forces a trade-off: a limit at the speed of light in fibre can be beaten by faster links, while one at the vacuum speed of light makes honest chips fail often. Protocol soundness ¹
  • A trusted landmark network must be built and secured, and who should operate it, under what oversight, is unsettled. Access & governance ^{1 4}
• Sampled inference recomputation
  • In tap-based retrofit designs, recording all inference traffic needs network taps and recomputation servers that can ingest it, in the worst case one recomputation-server network interface per inference front-end interface. Coverage & hidden compute. Waits on Network taps and certifiers ^{15 32}
  • In retrofit designs, the recomputation server must sit inside the prover's data centre, possibly under the prover's physical control, and still be protected from a compromised provider, which Amodo rates 'not on track'. Hardware trust ^{8 15}
  • No independent red-team of a recomputation consistency check has been published (the one independent attack study targets the weight-exfiltration bound), and Amodo rates recomputation red-teaming 'not started'. Adversarial validation ^{15 16}
  • Tolerance-based checks need calibration on trusted hardware and exact knowledge of the provider's sampling procedure, and in one prototype a sampling-implementation mismatch produced large spurious differences. Performance & compatibility ^{9 14}
  • The verifier needs the model weights, so checking a closed-weights model requires a trusted, confidential recomputation environment, which the retrofit designs place inside the prover's facility. Privacy & leakage ^{9 20 21}
• Deterministic and bit-exact inference
  • Batch-invariant kernels cost throughput: in Thinking Machines' Qwen3-8B test, an improved deterministic build took 42 s against 26 s for vLLM's default, and SGLang reports an average 34.35% slowdown on its FlashInfer and FlashAttention 3 backends. Performance & compatibility ^{22 24}
  • Coverage is incomplete: the bit-exact emulator targets dense blocks on NVIDIA GPUs and excludes mixture-of-experts inference and training, and vLLM's batch-invariant mode is in beta, with open work on AMD hardware and speculative decoding. Performance & compatibility ^{19 25 33}
  • Amodo's status page for the AI 2040 verification plan rates a reproducible inference stack for that plan as 'not started'. Performance & compatibility ¹⁵
  • Exact replay requires the prover to disclose weights, software versions, parallelism and batch sizes to whoever recomputes. Privacy & leakage ^{19 21}

From the family or selected implementation's record. ?

Model weights

Depends on the design for Sampled inference recomputation and Deterministic and bit-exact inference.

Not involved: Chip location verification.

Inputs and outputs

Depends on the design for Sampled inference recomputation and Deterministic and bit-exact inference.

Not involved: Chip location verification.

Training data

Not involved: Chip location verification, Sampled inference recomputation and Deterministic and bit-exact inference.

Chip location verification

• Proposed Lucid sovereignty (location) certificates Standard, Lucid Computing

Sampled inference recomputation

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Research demo DiFR (Divergence From Reference) Research prototype
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Proposed SASH confidential network logger Research prototype, Singapore AI Safety Hub (SASH)
• Operational use TOPLOC Open-source project, Prime Intellect

Deterministic and bit-exact inference

• Research demo Batch-invariant inference kernels (Thinking Machines) Open-source project, Thinking Machines Lab
• Operational use Verde and RepOps (Gensyn) Product, Gensyn
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute

1. Location Verification for AI Chips, A. Brass & O. Aarne (2024). Original
2. Location Verification for AI Chips (issue brief), A. Brass (2025). Original
3. Ping-based Location, Ulyssean (2025). Original
4. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
5. Sovereignty Certificates: draft specification, version 0.1.0, Sovereignty Certificates Working Group (2025). Original
6. GPU Fingerprinting for Location Verification, W. Tee & J. Happel (2026). Original
7. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
8. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
9. DiFR: Inference Verification Despite Nondeterminism, A. Karvonen et al. (2025). Original
10. TOPLOC: A Locality Sensitive Hashing Scheme for Trustless Verifiable Inference, J. M. Ong et al. (2025). Original
11. PrimeIntellect-ai/toploc (GitHub repository), Prime Intellect (2025). Original
12. INTELLECT-2: A Reasoning Model Trained Through Globally Decentralized Reinforcement Learning, Prime Intellect Team et al. (2025). Original
13. adamkarvonen/difr (GitHub repository), A. Karvonen (2025). Original
14. Scaling Recomputation Inference Verification, Amodo Design (2026). Original
15. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original
16. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
17. SYNTHETIC-2 Release: Four Million Collaboratively Generated Reasoning Traces, Prime Intellect (2025). Original
18. An Inference Verification Prototype — Stage 1, Amodo Design (2026). Original
19. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
20. Example Schemes for Verifying High-Stakes AI Agreements, Amodo Design (2026). Original
21. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
22. Defeating Nondeterminism in LLM Inference, H. He & Thinking Machines Lab (2025). Original
23. Hawkeye: Reproducing GPU-Level Non-Determinism, E. Badash et al. (2026). Original
24. Towards Deterministic Inference in SGLang and Reproducible RL Training, The SGLang Team (2025). Original
25. Batch Invariance (vLLM documentation), vLLM project (2026). Original
26. gensyn-ai/ree: Gensyn Reproducible Execution Environment (GitHub repository), Gensyn (2026). Original
27. EigenCloud Brings Verifiable AI to Mass Market with EigenAI and EigenCompute Launches, EigenCloud (2025). Original
28. Building Delphi: Pricing, Settlement, and Agentic Trading, D. Jedamski (2026). Original
29. Reproducible Execution Environment (REE) (Gensyn documentation), Gensyn (2026). Original
30. What is Delphi? (Delphi documentation), Gensyn (2026). Original
31. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
32. Verification Plan, R. Dean (2026). Original
33. [Feature]: Batch Invariant Feature and Performance Optimization (vLLM issue #27433), vLLM project contributors (2025). Original