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A verification proposal from the AI Verification Tech Map, from its records of 2026-10-08. https://trustbutveri.fyi/explorer/?mechanisms=M-0015,M-0002&tested=analysis&hide=training

Claims

Mechanisms2

Filters:×× 23 of 25 match · Clear

Applied filters: Attack testing: Published analysis; Keep hidden from the verifier: training data. Not set (Any): Prover, Verifier devices on site, Prover cooperation, Chips, Minimum readiness.

Analysis

Applied filters: Attack testing: Published analysis; Keep hidden from the verifier: training data. Not set (Any): Prover, Verifier devices on site, Prover cooperation, Chips, Minimum readiness.

MechanismReadinessOpen flaws
Memory wiping and proofs of secure erasure R12 significant1 minor
Deterministic and bit-exact inference R31 significant1 minor
  • Open flaws: n critical n significant n minor
Claim coverageNo claims yet

Add claims to see which ones the mechanisms address.

Properties1 in production · 2 built for an adversarial prover
In production
Attack testing2 mechanisms with published testing

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

Limits1 not yet demonstrated · 2 mechanisms with open significant findings
Open significant flaws
3 flaws in 2 mechanisms
  • Memory the wipe cannot reach in Memory wiping and proofs of secure erasure

    Amodo's inventory of a GB200 system lists many memory stores beyond GPU HBM and host DRAM. It notes that SSD controller DRAM sits on a private bus that host commands cannot read or write, and that its optimized algorithm leaves 25 GiB of HBM unattested. It also asks how switch memory could be wiped. 5 6

    Open question · Significant · Open. On the record

  • Outside help during challenges in Memory wiping and proofs of secure erasure

    Classic proofs of secure erasure assume the device is isolated during the protocol. Bursuc et al. relax this to a bound on how close a helper can be, enforced by round-trip times. In data centres, remote memory access has round trips of about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview therefore says verification depends on ruling out RDMA by latency or physical disconnection. 3 4

    Theoretical argument · Significant · Open. On the record

    Related mechanism R2 Timed challenge-response and memory-occupation challenges: Timed challenges bound how far away a helper can be by how quickly it must answer. A pointer, not evidence that this flaw is mitigated. Add

    Related mechanism R2 Bandwidth limits and compartmentalization: Removing or capping links between groups of accelerators limits remote memory access during a challenge. A pointer, not evidence that this flaw is mitigated. Add

  • Cross-hardware replay relies on reverse-engineered, closed behaviour in Deterministic and bit-exact inference

    Emulating one GPU's rounding on another requires reverse-engineering tensor-core arithmetic and modelling proprietary kernel choices. Hawkeye covers a subset of NVIDIA architectures and states that attention and other higher-level operations need further reverse engineering. For the bit-exact emulator, a proprietary Hopper kernel family is an open edge case. 9 11

    Open question · Significant · Open. On the record

Open minor flaws
2 mechanisms with minor findings
  • Gap between erased and total memory in Memory wiping and proofs of secure erasure

    Bursuc et al. note that memory left between the erased region and the device's full memory could hold data, and that their bounds are tighter only against a restricted adversary. 3

    Theoretical argument · Minor · Open. On the record

  • Some kernels remain genuinely nondeterministic in Deterministic and bit-exact inference

    The bit-exact work separates kernels that are deterministic but not batch-invariant from truly nondeterministic ones that use atomic functions. Some integer de-quantization kernels use atomic additions and remain nondeterministic, so exact replay needs backends that avoid them. 9

    Open question · Minor · Open. On the record

Possible additions2 for open flaws · 1 for dependencies

Mechanisms on the map that are not in the proposal. Pointers, not recommendations.

    • Bears on the open significant flaw “Outside help during challenges” in Memory wiping and proofs of secure erasure. Removing or capping links between groups of accelerators limits remote memory access during a challenge.
    • Bears on the open significant flaw “Outside help during challenges” in Memory wiping and proofs of secure erasure. Timed challenges bound how far away a helper can be by how quickly it must answer.
    • Memory wiping and proofs of secure erasure waits on it. Timed challenges must exclude remote memory and other helpers.
Dependencies1 missing prerequisite · 7 blockers
Missing prerequisites
Blockers
7 blockers recorded
  • Memory wiping and proofs of secure erasure
    • Wipes take time: tens of minutes for a pod's volatile memory and hours for SSDs, displacing work. Performance & compatibility 4 5 6
    • Timed challenges must exclude remote memory and other helpers. Coverage & hidden compute. Waits on Timed challenge-response and memory-occupation challenges 3 4
    • All memory stores in a system must be inventoried and wiped at the same time. Coverage & hidden compute 5
  • Deterministic and bit-exact inference
    • Batch-invariant kernels cost throughput: in Thinking Machines' Qwen3-8B test, an improved deterministic build took 42 s against 26 s for vLLM's default, and SGLang reports an average 34.35% slowdown on its FlashInfer and FlashAttention 3 backends. Performance & compatibility 10 12
    • Coverage is incomplete: the bit-exact emulator targets dense blocks on NVIDIA GPUs and excludes mixture-of-experts inference and training, and vLLM's batch-invariant mode is in beta, with open work on AMD hardware and speculative decoding. Performance & compatibility 9 13 19
    • Amodo's status page for the AI 2040 verification plan rates a reproducible inference stack for that plan as 'not started'. Performance & compatibility 20
    • Exact replay requires the prover to disclose weights, software versions, parallelism and batch sizes to whoever recomputes. Privacy & leakage 4 9
What the verifier sees1 depend on design

From the family or selected implementation's record.

Model weights

Depends on the design for Deterministic and bit-exact inference.

Not involved: Memory wiping and proofs of secure erasure.

Inputs and outputs

Depends on the design for Deterministic and bit-exact inference.

Not involved: Memory wiping and proofs of secure erasure.

Exposure notes
Implementations4 systems
Memory wiping and proofs of secure erasure
Deterministic and bit-exact inference
Sources20 cited
  1. Verification Plan, R. Dean (2026). Original
  2. Secure Code Update for Embedded Devices via Proofs of Secure Erasure, D. Perito & G. Tsudik (2010). Original
  3. Software-Based Memory Erasure with Relaxed Isolation Requirements, S. Bursuc et al. (2024). Original
  4. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
  5. Memory Wipes - Performance Analysis, Amodo Design (2026). Original
  6. Improving Disk Wiping Speed for Memory Wipes, Amodo Design (2026). Original
  7. Amodo-Design/PoSE-Memory-Wiping (GitHub repository), Amodo Design (2026). Original
  8. Empirical Evaluation of Memory-Erasure Protocols, R. Gil-Pons et al. (2025). Original
  9. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
  10. Defeating Nondeterminism in LLM Inference, H. He & Thinking Machines Lab (2025). Original
  11. Hawkeye: Reproducing GPU-Level Non-Determinism, E. Badash et al. (2026). Original
  12. Towards Deterministic Inference in SGLang and Reproducible RL Training, The SGLang Team (2025). Original
  13. Batch Invariance (vLLM documentation), vLLM project (2026). Original
  14. gensyn-ai/ree: Gensyn Reproducible Execution Environment (GitHub repository), Gensyn (2026). Original
  15. EigenCloud Brings Verifiable AI to Mass Market with EigenAI and EigenCompute Launches, EigenCloud (2025). Original
  16. Building Delphi: Pricing, Settlement, and Agentic Trading, D. Jedamski (2026). Original
  17. Reproducible Execution Environment (REE) (Gensyn documentation), Gensyn (2026). Original
  18. What is Delphi? (Delphi documentation), Gensyn (2026). Original
  19. [Feature]: Batch Invariant Feature and Performance Optimization (vLLM issue #27433), vLLM project contributors (2025). Original
  20. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original

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Filter mechanisms

Filters apply to mechanisms only. They describe the setting a proposal is for, and all are off by default. A mechanism that a filter rules out is flagged and does not count towards claim coverage. Selected implementations use their own record fields. A match means not excluded; conditional or unspecified exposure stays with a note. Passing a filter does not establish that the assumptions hold in a deployment.

23 of 25 mechanisms match · Clear all

Prover

How far can the party being checked be trusted?

The prover is the party being checked. Semi-trusted designs rely on part of its stack: usually the chip vendor's hardware root of trust, its firmware or counters, or its supply-chain records. Adversarial designs aim to hold even if it cheats wherever the checks allow, within their stated assumptions.

Keeps mechanisms whose threat model holds against at least this prover. Adversarial is the strongest assumption. Definitions

Verifier devices on site

May the verifier install its own hardware at the prover's sites?

Some mechanisms need a device the verifier owns or trusts at the prover's facility, such as a network tap, a bandwidth limiter or a sealed sensor. Choose Not allowed when the setting rules that out. Inspectors are not covered.

"Not allowed" removes mechanisms that need a retrofit device, such as a network tap or a sealed sensor. Definitions

Prover cooperation

How much must the prover take part?

Required: the prover takes part, for example by logging requests, producing proofs or opening records. Partial: some access, such as installing a device. Not required: works from outside, such as satellite imagery.

"Partial at most" removes mechanisms that need the prover's active participation. "Not required" keeps only those that work without it. Definitions

Chips

May the proposal depend on new chip designs?

New chip features take years to reach a deployed fleet and cover only chips made after they ship. Mechanisms that use shipping features, such as trusted execution environments or performance counters, stay.

"Existing chips only" removes mechanisms that need changes to future chip designs. Definitions

Minimum readiness

How mature must each mechanism be?

A level describes the public evidence for a mechanism's stated use, not its cost or feasibility. R3 can still have open critical flaws.

Keeps mechanisms whose readiness level is at least this one. Definitions

Attack testing

How hard has each mechanism been attacked in public?

The strongest published attempt to break the mechanism for its verification use: a security analysis, red-teaming by its developers or collaborators, or a red team independent of them.

Keeps mechanisms whose strongest published attack testing is at least this. Definitions

Keep hidden from the verifier

What must the verifier never see? Choose any.

Model weights: the checked model's parameters. Inputs and outputs: the requests a deployed model serves and its responses. Training data: what a model was trained on. Each mechanism's exposure is the editors' reading of its record: shown, depends on the design (kept, with a note), hidden, not involved, or unspecified for a selected implementation. Code and configuration are not covered yet.

Removes mechanisms that show the asset to the verifier. Conditional or unspecified exposure stays with a note and needs checking against the privacy requirement.

Claims

A claim is something one party wants to verify about another party's AI hardware or software. Each claim's number shows how the proposal addresses it.

  • Addressed. A mechanism in the proposal is aimed at this claim and is not excluded by the filters.
  • Partly addressed. Only supporting mechanisms, or mechanisms aimed at it that the filters exclude.
  • Unaddressed. No mechanism in the proposal addresses this claim.

Addressed means a mechanism in the proposal is aimed at the claim and is not excluded by your filters. It does not mean the claim is verified: check its assessed use, readiness, assumptions and open flaws.

All claims

Mechanisms

A mechanism is a general technique for verifying claims. Its badge is its readiness level for its stated use. An optional implementation choice narrows its assumptions, assessed use and claim links to that record. Lines join it to the claims it addresses. Click a line for details.Under its name it lists the claims it is aimed at or supports.

  • Aimed at the claim: verifying it is a direct purpose of the mechanism.
  • Supports the claim: helps verify it without being aimed at it.
  • Faint: excluded by your filters, so it does not count towards claim coverage.

All mechanisms

Overview

One row per mechanism in the proposal. Every mark comes from that mechanism's record, as listed in the panels below; what the verifier sees is the editors' reading of the record's text. Flaw counts are per mechanism. Summary counts name mechanisms with open findings, not a sum of attacks. Choosing an implementation narrows each row to that record's assessed use; family findings remain as context.

What the verifier sees

For model weights, inputs and outputs, and training data. This is the editors' reading of each mechanism's record (its threat model, how it works and its limitations), not a field of the record. Shown: the verifier sees it. Depends: on the design or variant, or the verifier sees only samples. Hidden: the verifier sees only commitments, hashes, proofs or results. Not involved: the record does not handle it. Unspecified: the selected implementation has no asset-specific assessment here.

Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open flaw or a dependency. They are pointers, not recommendations: each brings its own readiness level and flaws, and none is claimed to close a flaw. Links from flaws are the editors' reading of the two records.

Start from a published design

Choosing a design loads the mechanisms its record realises or depends on. If the proposal has no claims yet, it also loads the claims that record says the design addresses.

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