Proposal Explorer

Add claims to see which ones the mechanisms address.

Operational use

• Operational use Deterministic and bit-exact inference for reproducing open-model inference from receipts in Gensyn's information-market service

Built for an adversarial prover

Memory wiping and proofs of secure erasure, Deterministic and bit-exact inference and Side-channel suppression for isolated facilities

No new hardware needed

Memory wiping and proofs of secure erasure and Deterministic and bit-exact inference

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Memory wiping and proofs of secure erasure: Analysis
• Deterministic and bit-exact inference: Analysis
• Side-channel suppression for isolated facilities: Analysis

Open significant failures

1 failure in 1 mechanism

• Outside help during challenges in Memory wiping and proofs of secure erasure

  Classic proofs of secure erasure assume the device is isolated during the protocol. Bursuc et al. relax this to a bound on how close a helper can be, enforced by round-trip times. In data centres, remote memory access has round trips of about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview therefore says verification depends on ruling out RDMA by latency or physical disconnection. ^{3 4}

  Known failure · Theoretical argument · Significant · Open. On the record

  Related mechanism Research demo Timed challenge-response and memory-occupation challenges: Timed challenges bound how far away a helper can be by how quickly it must answer. A pointer, not evidence that this failure is mitigated. Add

  Related mechanism Research demo Bandwidth limits and compartmentalization: Removing or capping links between groups of accelerators limits remote memory access during a challenge. A pointer, not evidence that this failure is mitigated. Add

Scope limitations

• Memory the wipe cannot reach in Memory wiping and proofs of secure erasure

  Amodo's inventory of a GB200 system lists many memory stores beyond GPU HBM and host DRAM. It notes that SSD controller DRAM sits on a private bus that host commands cannot read or write, and that its optimized algorithm leaves 25 GiB of HBM unattested. It also asks how switch memory could be wiped. ^{5 6}

  Scope limitation · Open question. On the record

• Gap between erased and total memory in Memory wiping and proofs of secure erasure

  Bursuc et al. note that memory left between the erased region and the device's full memory could hold data, and that their bounds are tighter only against a restricted adversary. ³

  Scope limitation · Theoretical argument. On the record

• Some kernels remain genuinely nondeterministic in Deterministic and bit-exact inference

  The bit-exact work separates kernels that are deterministic but not batch-invariant from truly nondeterministic ones that use atomic functions. Some integer de-quantization kernels use atomic additions and remain nondeterministic, so exact replay needs backends that avoid them. ⁹

  Scope limitation · Open question. On the record

• Cross-hardware replay relies on reverse-engineered, closed behaviour in Deterministic and bit-exact inference

  Emulating one GPU's rounding on another requires reverse-engineering tensor-core arithmetic and modelling proprietary kernel choices. Hawkeye covers a subset of NVIDIA architectures and states that attention and other higher-level operations need further reverse engineering. For the bit-exact emulator, a proprietary Hopper kernel family is an open edge case. ^{9 11}

  Scope limitation · Open question. On the record

• Openings for airflow, power and optics weaken shielding in Side-channel suppression for isolated facilities

  Cankaya notes that keeping attenuation high while passing high-power airflow, cabling and optical links adds complexity beyond existing shielded-enclosure specifications. ¹⁹

  Scope limitation · Theoretical argument. On the record

Open questions

• Supply-chain implants may evade inspection in Side-channel suppression for isolated facilities

  Cankaya identifies malicious hardware embedded deep in purchased components as a residual risk that visual inspection and disassembly may not catch. He notes that radiographic examination under high-security standards could mitigate it. ¹⁹

  Open question · Theoretical argument. On the record

• Inspection assumptions may not hold in Side-channel suppression for isolated facilities

  The design's statistical argument assumes that visual or disassembly inspection catches every flaw that is present in a sampled unit. Cankaya is unsure whether destructive teardowns are defence-dominant or offence-dominant. ¹⁹

  Open question · Open question. On the record

Not yet demonstrated

Proposed Memory wiping and proofs of secure erasure and Proposed Side-channel suppression for isolated facilities

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Research demo Bandwidth limits and compartmentalization Add
  • Bears on the open significant failure “Outside help during challenges” in Memory wiping and proofs of secure erasure. Removing or capping links between groups of accelerators limits remote memory access during a challenge.
• Research demo Timed challenge-response and memory-occupation challenges Add
  • Bears on the open significant failure “Outside help during challenges” in Memory wiping and proofs of secure erasure. Timed challenges bound how far away a helper can be by how quickly it must answer.
  • Memory wiping and proofs of secure erasure waits on it. Timed challenges must exclude remote memory and other helpers.

Missing prerequisites

• Research demo Timed challenge-response and memory-occupation challenges needed by Memory wiping and proofs of secure erasure Add

Blockers

9 blockers recorded

• Memory wiping and proofs of secure erasure
  • Wipes take time: tens of minutes for a pod's volatile memory and hours for SSDs, displacing work. Performance & compatibility ^{4 5 6}
  • Timed challenges must exclude remote memory and other helpers. Coverage & hidden compute. Waits on Timed challenge-response and memory-occupation challenges ^{3 4}
  • All memory stores in a system must be inventoried and wiped at the same time. Coverage & hidden compute ⁵
• Deterministic and bit-exact inference
  • Batch-invariant kernels cost throughput: in Thinking Machines' Qwen3-8B test, an improved deterministic build took 42 s against 26 s for vLLM's default, and SGLang reports an average 34.35% slowdown on its FlashInfer and FlashAttention 3 backends. Performance & compatibility ^{10 12}
  • Coverage is incomplete: the bit-exact emulator targets dense blocks on NVIDIA GPUs and excludes mixture-of-experts inference and training, and vLLM's batch-invariant mode is in beta, with open work on AMD hardware and speculative decoding. Performance & compatibility ^{9 13 20}
  • Amodo's status page for the AI 2040 verification plan rates a reproducible inference stack for that plan as 'not started'. Performance & compatibility ²¹
  • Exact replay requires the prover to disclose weights, software versions, parallelism and batch sizes to whoever recomputes. Privacy & leakage ^{4 9}
• Side-channel suppression for isolated facilities
  • No prototype or red-team exists; the design is a first-pass viability study. Adversarial validation ¹⁹
  • Volume costs of TEMPEST-grade power-line filters are uncertain, because existing products are mostly made to order. Performance & compatibility ¹⁹

From the family or selected implementation's record. ?

Model weights

Depends on the design for Deterministic and bit-exact inference.

Not involved: Memory wiping and proofs of secure erasure and Side-channel suppression for isolated facilities.

Inputs and outputs

Depends on the design for Deterministic and bit-exact inference.

Not involved: Memory wiping and proofs of secure erasure and Side-channel suppression for isolated facilities.

Training data

Not involved: Memory wiping and proofs of secure erasure, Deterministic and bit-exact inference and Side-channel suppression for isolated facilities.

Memory wiping and proofs of secure erasure

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute

Deterministic and bit-exact inference

• Research demo Batch-invariant inference kernels (Thinking Machines) Open-source project, Thinking Machines Lab
• Operational use Verde and RepOps (Gensyn) Product, Gensyn
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute

Side-channel suppression for isolated facilities

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Proposed RAND secure inference data center (SIDC) design Proposed architecture, RAND

1. Verification Plan, R. Dean (2026). Original
2. Secure Code Update for Embedded Devices via Proofs of Secure Erasure, D. Perito & G. Tsudik (2010). Original
3. Software-Based Memory Erasure with Relaxed Isolation Requirements, S. Bursuc et al. (2024). Original
4. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
5. Memory Wipes - Performance Analysis, Amodo Design (2026). Original
6. Improving Disk Wiping Speed for Memory Wipes, Amodo Design (2026). Original
7. Amodo-Design/PoSE-Memory-Wiping (GitHub repository), Amodo Design (2026). Original
8. Empirical Evaluation of Memory-Erasure Protocols, R. Gil-Pons et al. (2025). Original
9. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
10. Defeating Nondeterminism in LLM Inference, H. He & Thinking Machines Lab (2025). Original
11. Hawkeye: Reproducing GPU-Level Non-Determinism, E. Badash et al. (2026). Original
12. Towards Deterministic Inference in SGLang and Reproducible RL Training, The SGLang Team (2025). Original
13. Batch Invariance (vLLM documentation), vLLM project (2026). Original
14. gensyn-ai/ree: Gensyn Reproducible Execution Environment (GitHub repository), Gensyn (2026). Original
15. EigenCloud Brings Verifiable AI to Mass Market with EigenAI and EigenCompute Launches, EigenCloud (2025). Original
16. Building Delphi: Pricing, Settlement, and Agentic Trading, D. Jedamski (2026). Original
17. Reproducible Execution Environment (REE) (Gensyn documentation), Gensyn (2026). Original
18. What is Delphi? (Delphi documentation), Gensyn (2026). Original
19. Suppressing Side Channels in an Untrusted Data Center via Retrofitted Defenses, N. Cankaya (2026). Original
20. [Feature]: Batch Invariant Feature and Performance Optimization (vLLM issue #27433), vLLM project contributors (2025). Original
21. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original