Proposal Explorer

Add claims to see which ones the mechanisms address.

Operational use

• Operational use Deterministic and bit-exact inference for reproducing open-model inference from receipts in Gensyn's information-market service

Built for an adversarial prover

Bounding unexplained information in outputs and Deterministic and bit-exact inference

No new hardware needed

On-chip telemetry from timing, memory and performance counters and Deterministic and bit-exact inference

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Bounding unexplained information in outputs: Independent red-team
• On-chip telemetry from timing, memory and performance counters: Red-teamed
• Deterministic and bit-exact inference: Analysis

Open significant failures

3 failures in 2 mechanisms

• Prompt-controlled entropy inflation widens the covert channel in Bounding unexplained information in outputs

  Gumbel-based inference verification tolerates token choices that honest GPU nondeterminism could produce, and the size of that tolerated set grows with the model's output entropy. Kezins, an independent researcher, showed that an adversary who controls the prompt distribution can raise output entropy and roughly double the bits leaked per token. Across six models of 1 to 32 billion parameters, this cut the slowdown from 146–254 times under benign prompts to 60–118 times. Kezins argues that architectures built on the same unexplained-information bound inherit this attack surface, and recommends calibrating tolerances against local token entropy rather than benign traffic. ^{2 3}

  Known failure · Demonstrated attack · Significant · Open. On the record

  Related mechanism Operational use Deterministic and bit-exact inference: Bit-exact replay would remove the tolerance for numerical noise that sets the size of this channel. The record notes that it needs full hardware and software metadata. A pointer, not evidence that this failure is mitigated. In the proposal.

• Adversarially disguised fine-tuning partly evades classification in On-chip telemetry from timing, memory and performance counters

  Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware. ⁸

  Known failure · Demonstrated attack · Significant · Open. On the record

• Counters leak information about protected workloads in On-chip telemetry from timing, memory and performance counters

  Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality. ^{9 10}

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Information the declared computation explains is not bounded in Bounding unexplained information in outputs

  The bound limits unexplained bits only. Outputs that the declared computation fully explains can still carry valuable information: a compression study notes that an adversary with inference access can extract more proprietary information per bit than naive transmission allows. ^{1 4}

  Scope limitation · Theoretical argument. On the record

• Channels other than checked outputs are outside the bound in Bounding unexplained information in outputs

  The inference-verification scheme treats side channels as out of scope. A low-trust system design argues that suppressing physical covert bandwidth below kilobits per second is much more achievable than aiming for zero, and that a malicious device can leak one bit of information by deliberately outputting a wrong result. ^{2 5}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Side-channel suppression for isolated facilities: Physical side channels need separate suppression, which is this mechanism's purpose. A pointer, not evidence that this failure is mitigated. Add

• Software-read telemetry can be forged by the operator in On-chip telemetry from timing, memory and performance counters

  NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized. ^{6 8}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing. A pointer, not evidence that this failure is mitigated. Add

• Timing challenges do not identify the individual chip in On-chip telemetry from timing, memory and performance counters

  GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use. ⁶

  Scope limitation · Theoretical argument. On the record

• Some kernels remain genuinely nondeterministic in Deterministic and bit-exact inference

  The bit-exact work separates kernels that are deterministic but not batch-invariant from truly nondeterministic ones that use atomic functions. Some integer de-quantization kernels use atomic additions and remain nondeterministic, so exact replay needs backends that avoid them. ¹¹

  Scope limitation · Open question. On the record

• Cross-hardware replay relies on reverse-engineered, closed behaviour in Deterministic and bit-exact inference

  Emulating one GPU's rounding on another requires reverse-engineering tensor-core arithmetic and modelling proprietary kernel choices. Hawkeye covers a subset of NVIDIA architectures and states that attention and other higher-level operations need further reverse engineering. For the bit-exact emulator, a proprietary Hopper kernel family is an open edge case. ^{11 13}

  Scope limitation · Open question. On the record

Open questions

• The facility-level design is untested in Bounding unexplained information in outputs

  The compute-verification architecture is described with protocol details, potential attacks and prototyping plans, but no prototype results have been published. ¹

  Open question · Open question. On the record

• No quantified error rates or formal thresholds for timing primitives in On-chip telemetry from timing, memory and performance counters

  Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work. ⁶

  Open question · Open question. On the record

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Research demo Bandwidth limits and compartmentalization Add
  • Bounding unexplained information in outputs waits on it. The prover's compute must be isolated so that all traffic passes through the verifier's interlock; any unmonitored path voids the bound.
• Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors Add
  • On-chip telemetry from timing, memory and performance counters waits on it. Shipping accelerators need a tamper-resistant, authenticated telemetry path.
• Proposed Side-channel suppression for isolated facilities Add
  • Bounding unexplained information in outputs waits on it. Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target.
• Operational use Sampled inference recomputation Add
  • Bounding unexplained information in outputs depends on it.
• Operational use TEE remote attestation for AI workloads Add
  • On-chip telemetry from timing, memory and performance counters depends on it.
• Proposed Network taps and certifiers Add
  • Bounding unexplained information in outputs depends on it.

Missing prerequisites

• Operational use Sampled inference recomputation needed by Bounding unexplained information in outputs Add
• Research demo Bandwidth limits and compartmentalization needed by Bounding unexplained information in outputs Add
• Proposed Side-channel suppression for isolated facilities needed by Bounding unexplained information in outputs Add
• Proposed Network taps and certifiers needed by Bounding unexplained information in outputs Add
• Operational use TEE remote attestation for AI workloads needed by On-chip telemetry from timing, memory and performance counters Add

Blockers

13 blockers recorded

• Bounding unexplained information in outputs
  • The prover's compute must be isolated so that all traffic passes through the verifier's interlock; any unmonitored path voids the bound. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization ¹
  • Physical side channels need separate suppression, and one design treats a low residual bandwidth, rather than zero, as the realistic target. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ^{2 5}
  • Tolerance for numerical nondeterminism sets the size of the residual channel; bit-exact replay would remove it but needs full hardware and software metadata. Protocol soundness. Waits on Deterministic and bit-exact inference ^{3 5}
  • Recomputation over confidential weights and inputs needs a protected setting: prover recomputation in a verifier-controlled enclosure, verifier recomputation in a prover-controlled enclosure, or zero-knowledge proofs. Privacy & leakage ¹
  • No prototype of the facility-level architecture exists to red-team. Adversarial validation ¹
• On-chip telemetry from timing, memory and performance counters
  • Shipping accelerators need a tamper-resistant, authenticated telemetry path. Hardware trust. Waits on Hardware-enabled guarantees (flexHEG) and guarantee processors ^{7 8}
  • NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. Privacy & leakage ^{9 10}
  • Continuous challenge puzzles cost power and throughput on production workloads. Performance & compatibility ⁶
  • Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. Adversarial validation ⁸
• Deterministic and bit-exact inference
  • Batch-invariant kernels cost throughput: in Thinking Machines' Qwen3-8B test, an improved deterministic build took 42 s against 26 s for vLLM's default, and SGLang reports an average 34.35% slowdown on its FlashInfer and FlashAttention 3 backends. Performance & compatibility ^{12 14}
  • Coverage is incomplete: the bit-exact emulator targets dense blocks on NVIDIA GPUs and excludes mixture-of-experts inference and training, and vLLM's batch-invariant mode is in beta, with open work on AMD hardware and speculative decoding. Performance & compatibility ^{11 15 21}
  • Amodo's status page for the AI 2040 verification plan rates a reproducible inference stack for that plan as 'not started'. Performance & compatibility ²²
  • Exact replay requires the prover to disclose weights, software versions, parallelism and batch sizes to whoever recomputes. Privacy & leakage ^{5 11}

From the family or selected implementation's record. ?

Model weights

Depends on the design for Bounding unexplained information in outputs, On-chip telemetry from timing, memory and performance counters and Deterministic and bit-exact inference.

Inputs and outputs

Depends on the design for Bounding unexplained information in outputs, On-chip telemetry from timing, memory and performance counters and Deterministic and bit-exact inference.

Training data

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Bounding unexplained information in outputs and Deterministic and bit-exact inference.

Bounding unexplained information in outputs

None on the map

On-chip telemetry from timing, memory and performance counters

None on the map

Deterministic and bit-exact inference

• Research demo Batch-invariant inference kernels (Thinking Machines) Open-source project, Thinking Machines Lab
• Operational use Verde and RepOps (Gensyn) Product, Gensyn
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute

1. Verifying AI Compute by Bounding Unexplained Information Exfiltration, J. Petrie & Y. Mühlhäuser (2026). Original
2. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
3. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
4. Haiku to Opus in Just 10 bits: LLMs Unlock Large Compression Gains, R. Rinberg et al. (2026). Original
5. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
6. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
7. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). Original
8. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). Original
9. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
10. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original
11. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
12. Defeating Nondeterminism in LLM Inference, H. He & Thinking Machines Lab (2025). Original
13. Hawkeye: Reproducing GPU-Level Non-Determinism, E. Badash et al. (2026). Original
14. Towards Deterministic Inference in SGLang and Reproducible RL Training, The SGLang Team (2025). Original
15. Batch Invariance (vLLM documentation), vLLM project (2026). Original
16. gensyn-ai/ree: Gensyn Reproducible Execution Environment (GitHub repository), Gensyn (2026). Original
17. EigenCloud Brings Verifiable AI to Mass Market with EigenAI and EigenCompute Launches, EigenCloud (2025). Original
18. Building Delphi: Pricing, Settlement, and Agentic Trading, D. Jedamski (2026). Original
19. Reproducible Execution Environment (REE) (Gensyn documentation), Gensyn (2026). Original
20. What is Delphi? (Delphi documentation), Gensyn (2026). Original
21. [Feature]: Batch Invariant Feature and Performance Optimization (vLLM issue #27433), vLLM project contributors (2025). Original
22. AI 2040 Plan A — Verification SITREP, Amodo Design (2026). Original