Proposal Explorer

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Chip registries and manufacturing records

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Chip registries and manufacturing records: Analysis

Family findings

• Sampled inference recomputation

  Context for SASH confidential network logger. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there.

  • Tolerance for numerical noise leaves a covert channel in Sampled inference recomputation

    Schemes that accept approximate matches can put an upper bound on an adversary's covert bandwidth, but they cannot close the channel. The weight-exfiltration detector cut exfiltratable information to under 0.5%, not to zero, on a 30-billion-parameter mixture-of-experts model under benign prompt traffic. Its authors called the channel's size under adversarial prompts an open empirical question. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token. Across six models, that cut the slowdown from 146–254 times under benign prompts to 60–118 times. The attack widens the exfiltration bound. It does not target the check that outputs match the declared model. ^{8 9 10}

    Known failure · Demonstrated attack · Significant · Open. On the record

    Related mechanism Operational use Deterministic and bit-exact inference: Bit-exact inference would remove the numerical tolerance if exact replay can be deployed with the required weights and configuration. A pointer, not evidence that this failure is mitigated. Add

  • Only recorded traffic is checked in Sampled inference recomputation

    Recomputation checks that recorded, declared workloads are correct. It cannot show that the record is complete. The published schemes do not cover hidden workloads run on the same compute, or substituted work. Rinberg et al. say their exfiltration-detection scheme cannot stand alone. ^{9 11}

    Scope limitation · Theoretical argument. On the record

    Related mechanism Proposed Network taps and certifiers: Taps copy and hash all traffic on the monitored links, which bears on whether the traffic record is complete. They do not show what else ran on the same chips. A pointer, not evidence that this failure is mitigated. Add

  • Some inference optimizations are not covered in Sampled inference recomputation

    TOPLOC's authors state that it cannot detect speculative decoding in which a cheaper model does the decoding. They did not test whether it distinguishes types of key-value (KV) cache compression. DiFR was evaluated only on sampling from a single model. Its authors sketch an extension to one speculative-decoding algorithm but do not test it. ^{12 13}

    Known failure · Theoretical argument · Significant · Open. On the record

  • Mixed hardware widens the honest baseline in Sampled inference recomputation

    When honest reference runs span different GPU types, the spread of benign scores grows. In DiFR's tests on Qwen3-30B-A3B, pooling A100 and H200 runs left Token-DiFR unable to separate the two smallest tested changes, a temperature of 1.1 instead of 1.0 and a simulated top-2 sampling bug, at the target false-positive rate, while cross-entropy separated them. Matched provider and verifier environments, or pooling that weights rare large deviations, restored detection. ¹³

    Known failure · Open question · Minor · Open. On the record

Open significant failures

1 failure in 1 mechanism

• Documents and serial numbers can be forged in Chip registries and manufacturing records

  Avellar and Grunewald note that export documents can be forged, that companies can hide information behind obscure corporate structures, and that it may be possible to forge serial numbers on chips and racks. They recommend cryptographic attestation of a powered-on chip as an extra check. ²

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Records cover only chips that were recorded in Chip registries and manufacturing records

  A registry or commitment accounts only for chips entered into it. Cankaya asks how a verifier would know it had found all chips, or how much "dark compute" remains, and notes that a fraudulent original record would mean unregistered chips had been made in advance. Halstead and Larsen propose reconstructing earlier production by auditing upstream suppliers. ^{3 5}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Remote detection of data centres: Looks for large data centres that were never declared, which a registry cannot show. A pointer, not evidence that this failure is mitigated. Add

• Insiders could alter records before they are fixed in Chip registries and manufacturing records

  Cankaya argues that insiders who can photograph process secrets could also tamper with production records. A commitment makes changes after publication detectable, but it cannot show that the records were accurate when committed. ³

  Scope limitation · Theoretical argument. On the record

• Logger hardware supply chain in SASH confidential network logger

  The prototype uses a Raspberry Pi 5 as the logger, which SASH says locks the design into Broadcom and Arm supply chains. ⁶

  Scope limitation · Open question. On the record

Open questions

• Recomputation cluster security is not monitored in SASH confidential network logger

  SASH states that the current prototype has no means to monitor the security of the recomputation cluster, which holds a copy of the model and decides whether an alarm is raised. ⁶

  Open question · Open question. On the record

• Side channels not yet addressed in SASH confidential network logger

  SASH lists eliminating a wider range of side-channel vulnerabilities as future work. ⁶

  Open question · Open question. On the record

Not yet demonstrated

Proposed Chip registries and manufacturing records and Proposed Sampled inference recomputation

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Operational use Deterministic and bit-exact inference Add
  • Sampled inference recomputation waits on it. Exact-match recomputation requires reproducible inference.
• Research demo Tamper evidence for verifier devices Add
  • Sampled inference recomputation depends on it.

Missing prerequisites

• Operational use Deterministic and bit-exact inference needed by Sampled inference recomputation Add
• Research demo Tamper evidence for verifier devices needed by Sampled inference recomputation Add

Blockers

6 blockers recorded

• Chip registries and manufacturing records
  • No implementation of an AI chip registry has been publicly reported, and covering re-exports would need cooperation from re-exporters and foreign governments that may not be feasible everywhere. Access & governance ^{1 2}
  • Linking records to physical chips needs hard-to-spoof unique IDs and inspections. Hardware trust ^{1 2 3}
  • Chips produced before a registry starts must be reconstructed from supplier records. Coverage & hidden compute ^{3 5}
• Sampled inference recomputation
  • The planned FPGA logger has not yet been built. Hardware trust ⁶
  • The design has not been scaled to production traffic volumes. Performance & compatibility ⁶
  • Exact-match recomputation requires reproducible inference. Evidence binding. Waits on Deterministic and bit-exact inference ⁷

From the family or selected implementation's record. ?

Model weights

Not involved: Chip registries and manufacturing records.

Unspecified for Sampled inference recomputation. Check the implementation record.

Inputs and outputs

Not involved: Chip registries and manufacturing records.

Unspecified for Sampled inference recomputation. Check the implementation record.

Training data

Not involved: Chip registries and manufacturing records.

Unspecified for Sampled inference recomputation. Check the implementation record.

Chip registries and manufacturing records

None on the map

Sampled inference recomputation

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Research demo DiFR (Divergence From Reference) Research prototype
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Proposed SASH confidential network logger Research prototype, Singapore AI Safety Hub (SASH)
• Operational use TOPLOC Open-source project, Prime Intellect

1. Verifying International Agreements on AI: Six Layers of Verification for Rules on Large-Scale AI Development and Deployment, M. Baker et al. (2025). Original
2. Near-Term Verification Methods for AI Chip Exports, B. Avellar & E. Grunewald (2026). Original
3. TSMC most definitely has a golden record of all AI chips it made, N. Cankaya (2025). Original
4. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification, S. Ansari (2026). Original
5. Covert AI Projects, B. Halstead & T. Larsen (2026). Original
6. Internationalising AI Verification, Singapore AI Safety Hub (SASH) (2026). Original
7. inference-verification: Inference Verification Prototype, Singapore AI Safety Hub (SASH) (2026). Original
8. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
9. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
10. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
11. Example Schemes for Verifying High-Stakes AI Agreements, Amodo Design (2026). Original
12. TOPLOC: A Locality Sensitive Hashing Scheme for Trustless Verifiable Inference, J. M. Ong et al. (2025). Original
13. DiFR: Inference Verification Despite Nondeterminism, A. Karvonen et al. (2025). Original