Proposal Explorer

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Built for an adversarial prover

Sampled inference recomputation

No new hardware needed

Safeguard attestation and On-chip telemetry from timing, memory and performance counters

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Safeguard attestation: Analysis
• Sampled inference recomputation, Low-trust AI compute verification system overview: Analysis
• On-chip telemetry from timing, memory and performance counters: Red-teamed

Family findings

• Sampled inference recomputation

  Context for Low-trust AI compute verification system overview. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there.

  • Tolerance for numerical noise leaves a covert channel in Sampled inference recomputation

    Schemes that accept approximate matches can put an upper bound on an adversary's covert bandwidth, but they cannot close the channel. The weight-exfiltration detector cut exfiltratable information to under 0.5%, not to zero, on a 30-billion-parameter mixture-of-experts model under benign prompt traffic. Its authors called the channel's size under adversarial prompts an open empirical question. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token. Across six models, that cut the slowdown from 146–254 times under benign prompts to 60–118 times. The attack widens the exfiltration bound. It does not target the check that outputs match the declared model. ^{15 16 17}

    Known failure · Demonstrated attack · Significant · Open. On the record

    Related mechanism Operational use Deterministic and bit-exact inference: Bit-exact inference would remove the numerical tolerance if exact replay can be deployed with the required weights and configuration. A pointer, not evidence that this failure is mitigated. Add

  • Only recorded traffic is checked in Sampled inference recomputation

    Recomputation checks that recorded, declared workloads are correct. It cannot show that the record is complete. The published schemes do not cover hidden workloads run on the same compute, or substituted work. Rinberg et al. say their exfiltration-detection scheme cannot stand alone. ^{16 18}

    Scope limitation · Theoretical argument. On the record

    Related mechanism Proposed Network taps and certifiers: Taps copy and hash all traffic on the monitored links, which bears on whether the traffic record is complete. They do not show what else ran on the same chips. A pointer, not evidence that this failure is mitigated. Add

  • Some inference optimizations are not covered in Sampled inference recomputation

    TOPLOC's authors state that it cannot detect speculative decoding in which a cheaper model does the decoding. They did not test whether it distinguishes types of key-value (KV) cache compression. DiFR was evaluated only on sampling from a single model. Its authors sketch an extension to one speculative-decoding algorithm but do not test it. ^{19 20}

    Known failure · Theoretical argument · Significant · Open. On the record

  • Mixed hardware widens the honest baseline in Sampled inference recomputation

    When honest reference runs span different GPU types, the spread of benign scores grows. In DiFR's tests on Qwen3-30B-A3B, pooling A100 and H200 runs left Token-DiFR unable to separate the two smallest tested changes, a temperature of 1.1 instead of 1.0 and a simulated top-2 sampling bug, at the target false-positive rate, while cross-entropy separated them. Matched provider and verifier environments, or pooling that weights rare large deviations, restored detection. ²⁰

    Known failure · Open question · Minor · Open. On the record

Open significant failures

4 failures in 2 mechanisms

• Components outside the attested boundary in Safeguard attestation

  In the proof-of-guardrail experiments, the guardrail model and the agent's backend model were both reached through external APIs, and the authors leave the decision to trust those APIs to the verifier. The measured wrapper must also have no vulnerability that lets the unmeasured agent bypass the guardrail, for example by executing arbitrary commands inside the enclave. The code's README states that the enclave does not currently restrict the agent's arbitrary command execution, which could be used to bypass guardrails. ^{1 2}

  Known failure · Theoretical argument · Significant · Open. On the record

• Memory-bus interposition extracts attestation keys and forges attestations in Safeguard attestation

  Applies to variants using the affected Intel or AMD trust roots. PAL*M excludes physical attacks. A TDX-backed safeguard claim against a physical host attacker would be defeated, but these studies do not demonstrate a break of the AWS Nitro proof-of-guardrail prototype or of verifier-side recomputation.

  The TEE findings cover DDR5 attacks on Intel TDX, the H100 relay demonstration, DDR4 attacks on AMD SEV-SNP, and software-only SEV-SNP forgery before AMD's fixes. These are inherited hardware limits; a governance analysis explains why physical access matters in a treaty setting. ^{1 4 7 8 9 10 11 12 13}

  Response: Intel and AMD place the physical attack class outside their threat models, according to the researchers. AMD reports firmware fixes for RMPocalypse.

  Known failure · Demonstrated attack · Significant · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this failure is mitigated. Add

• Adversarially disguised fine-tuning partly evades classification in On-chip telemetry from timing, memory and performance counters

  Across 20 evasion strategy families in five monitor-evader rounds, the classifier's accuracy against the most challenging disguised workloads held out from training was 43–87%. White-box LoRA fine-tuning was the only evasion family detected less than half the time. The evaluation covered single nodes, PyTorch-level evasion and NVIDIA hardware. ²³

  Known failure · Demonstrated attack · Significant · Open. On the record

• Counters leak information about protected workloads in On-chip telemetry from timing, memory and performance counters

  Performance counters have been used as a side channel against TEEs, for example in CounterSEVeillance. NVIDIA disables performance counters in full confidential-computing mode, stating that they could provide an avenue for side-channel attacks. Richer counters for verification therefore pull against confidentiality. ^{9 24}

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Attestation shows a safeguard ran, not that it is effective in Safeguard attestation

  Proof of guardrail ensures that the guardrail executed, but the guardrail can still err or be jailbroken. Because the guardrail must be open source, a malicious developer can attack it with jailbreaks while still presenting a valid proof. In the authors' evaluation, Llama Guard 3 reached an F1 score of 0.56 on the unsafe class of the ToxicChat dataset. The authors state that proof of guardrail should not be interpreted or advertised as proof of safety. ¹

  Scope limitation · Theoretical argument. On the record

• Selective attestation leaves traffic uncovered in Safeguard attestation

  Attestations are issued per response. In the prototype, the agent offers them when it receives high-stakes questions, so nothing shows that unattested traffic went through the same path. PAL*M's authors note that a prover could cherry-pick favourable executions, and suggest verifier-published nonces or requesting only session-level proofs. A governance analysis notes that auditors also need assurance that all activity is accounted for, since a host could start a second confidential virtual machine that bypasses monitoring. ^{1 4 9}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Research demo On-chip telemetry from timing, memory and performance counters: On-chip counters are a proposed route to evidence about everything a chip runs, including a second virtual machine that skips the safeguard. A pointer, not evidence that this failure is mitigated. In the proposal.

• Measurements may omit behaviour-relevant configuration or runtime changes in Safeguard attestation

  Every component that influences inference behaviour must be covered by the launch measurement, including feature flags, environment variables and invocation arguments. A launch measurement also does not show that a program keeps running as measured if the kernel is later compromised. ⁹

  Scope limitation · Theoretical argument. On the record

• Mismatches cannot be attributed to cheating or error in Low-trust AI compute verification system overview

  A failed hash or replay does not show whether it came from an evasion attempt, a random bit flip or an evaluation error. The author notes that if detected anomalies can plausibly be waved off as malfunctions, deterrence becomes less effective, so the parties need an agreed escalation procedure that ends in attribution. ¹³

  Scope limitation · Theoretical argument. On the record

• Software-read telemetry can be forged by the operator in On-chip telemetry from timing, memory and performance counters

  NVML-based classification assumes trustworthy telemetry. Without a tamper-resistant read path, an authenticated telemetry channel and secure boot of the monitoring software, an operator who controls the full software stack could forge counter values. Monfared et al. start from the same premise: current GPUs expose little trusted telemetry and can be modified or virtualized. ^{21 23}

  Scope limitation · Theoretical argument. On the record

  Related mechanism Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors: A guarantee processor on the chip would give the tamper-resistant, authenticated telemetry path the flaw says is missing. A pointer, not evidence that this failure is mitigated. Add

• Timing challenges do not identify the individual chip in On-chip telemetry from timing, memory and performance counters

  GEMM and VDF challenges can be answered by identical GPUs elsewhere, and floating-point fingerprints distinguish GPU models, not individual devices. GPU virtualization adds timing leakage that prevents attributing compute use. ²¹

  Scope limitation · Theoretical argument. On the record

Open questions

• Inspector agents may be manipulable in Low-trust AI compute verification system overview

  Automated compliance screening with LLM-based inspector agents must resist prompt-injection attacks. Adversarially trained systems might hide malicious actions with steganography, which makes backdoor detection an open problem. ¹³

  Open question · Open question. On the record

• No quantified error rates or formal thresholds for timing primitives in On-chip telemetry from timing, memory and performance counters

  Monfared et al. state that false-positive and false-negative rates are not quantified and leave hardware-specific formal thresholds to future work. ²¹

  Open question · Open question. On the record

Open minor failures

1 mechanism with minor failures

• Deliberate faults leak a bit each in Low-trust AI compute verification system overview

  A malicious device can leak one bit by deliberately outputting a wrong result, which blocks a disclosure when the cross-comparison fails. The design therefore needs a pre-agreed budget of tolerated faults. ¹³

  Known failure · Theoretical argument · Minor · Open. On the record

Not yet demonstrated

Proposed Sampled inference recomputation

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Proposed Hardware-enabled guarantees (flexHEG) and guarantee processors Add
  • Bears on the open significant failure “Memory-bus interposition extracts attestation keys and forges attestations” in Safeguard attestation. A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically.
  • On-chip telemetry from timing, memory and performance counters waits on it. Shipping accelerators need a tamper-resistant, authenticated telemetry path.
• Operational use Deterministic and bit-exact inference Add
  • Sampled inference recomputation waits on it. Exact replay needs complete hardware and software metadata, and the tolerable slowdown from emulation is an open question.
• Operational use Hardware-attested weight binding Add
  • Safeguard attestation waits on it. Safeguard evidence must be bound to the model actually served, which depends on model-identity attestation.
• Operational use TEE remote attestation for AI workloads Add
  • Safeguard attestation waits on it. Frontier model inference typically needs several GPUs, GPU confidential computing is less mature than CPU support, and CPU inference, which an enclave prototype had to use, ran about 100 times slower than GPU inference.
  • Safeguard attestation waits on it. Trust rests on a small number of hardware vendors, and a per-CPU Intel attestation key has been extracted by physical attack.
  • On-chip telemetry from timing, memory and performance counters depends on it.
• Research demo Tamper evidence for verifier devices Add
  • Sampled inference recomputation waits on it. Tamper-evident, rapidly mass-manufacturable and retrofittable enclosures for side-channel defence are an open research question, and physical security against covert communication in every monitored data centre is challenging.
• Research demo Timed challenge-response and memory-occupation challenges Add
  • Sampled inference recomputation waits on it. Distinguishing one server's DRAM contents from another's by challenge-response timing, and a general challenge-response protocol for diverse data types, are open.
• Proposed Network taps and certifiers Add
  • Sampled inference recomputation waits on it. Empirical feasibility of passive optical splitting at 53–112 GBaud under realistic conditions is an open question.
• Proposed Side-channel suppression for isolated facilities Add
  • Sampled inference recomputation waits on it. A mass-manufacturable, good-enough side-channel defence, particularly power-line filtering, has not been constructed or red-teamed.

Missing prerequisites

• Operational use TEE remote attestation for AI workloads needed by Safeguard attestation and On-chip telemetry from timing, memory and performance counters Add
• Operational use Hardware-attested weight binding needed by Safeguard attestation Add
• Proposed Network taps and certifiers needed by Sampled inference recomputation Add
• Operational use Deterministic and bit-exact inference needed by Sampled inference recomputation Add

Shared foundations

• TEE remote attestation for AI workloads relied on by Safeguard attestation and On-chip telemetry from timing, memory and performance counters

Blockers

15 blockers recorded

• Safeguard attestation
  • No published design shows that all of a provider's traffic passes through the attested safeguard path; current evidence covers individual attested responses. Coverage & hidden compute ^{1 9}
  • Frontier model inference typically needs several GPUs, GPU confidential computing is less mature than CPU support, and CPU inference, which an enclave prototype had to use, ran about 100 times slower than GPU inference. Performance & compatibility. Waits on TEE remote attestation for AI workloads ^{9 25}
  • Trust rests on a small number of hardware vendors, and a per-CPU Intel attestation key has been extracted by physical attack. Hardware trust. Waits on TEE remote attestation for AI workloads ^{7 9}
  • Safeguard evidence must be bound to the model actually served, which depends on model-identity attestation. Evidence binding. Waits on Hardware-attested weight binding ^{25 26}
  • No independent red-team or audit of a safeguard-attestation system has been published, and the available prototypes are described by their authors as proofs of concept that have not been stress-tested by a counterparty. Adversarial validation ^{2 6}
• Sampled inference recomputation
  • Empirical feasibility of passive optical splitting at 53–112 GBaud under realistic conditions is an open question. Performance & compatibility. Waits on Network taps and certifiers ¹³
  • Exact replay needs complete hardware and software metadata, and the tolerable slowdown from emulation is an open question. Performance & compatibility. Waits on Deterministic and bit-exact inference ¹³
  • Tamper-evident, rapidly mass-manufacturable and retrofittable enclosures for side-channel defence are an open research question, and physical security against covert communication in every monitored data centre is challenging. Hardware trust. Waits on Tamper evidence for verifier devices ¹³
  • A mass-manufacturable, good-enough side-channel defence, particularly power-line filtering, has not been constructed or red-teamed. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ¹³
  • Distinguishing one server's DRAM contents from another's by challenge-response timing, and a general challenge-response protocol for diverse data types, are open. Coverage & hidden compute. Waits on Timed challenge-response and memory-occupation challenges ¹³
  • The threat model is under-developed and needs input from cybersecurity and AI threat-modelling experts. Adversarial validation ¹³
• On-chip telemetry from timing, memory and performance counters
  • Shipping accelerators need a tamper-resistant, authenticated telemetry path. Hardware trust. Waits on Hardware-enabled guarantees (flexHEG) and guarantee processors ^{22 23}
  • NVIDIA's full confidential-computing mode disables the hardware performance counters its profiling tools use, so telemetry that needs them conflicts with it. Privacy & leakage ^{9 24}
  • Continuous challenge puzzles cost power and throughput on production workloads. Performance & compatibility ²¹
  • Evaluation has not gone beyond single nodes, framework-level evasion and one vendor's hardware. Adversarial validation ²³

From the family or selected implementation's record. ?

Model weights

Depends on the design for Safeguard attestation and On-chip telemetry from timing, memory and performance counters.

Unspecified for Sampled inference recomputation. Check the implementation record.

Inputs and outputs

Depends on the design for Safeguard attestation and On-chip telemetry from timing, memory and performance counters.

Unspecified for Sampled inference recomputation. Check the implementation record.

Training data

Depends on the design for On-chip telemetry from timing, memory and performance counters.

Not involved: Safeguard attestation.

Unspecified for Sampled inference recomputation. Check the implementation record.

Safeguard attestation

None on the map

Sampled inference recomputation

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Research demo DiFR (Divergence From Reference) Research prototype
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Proposed SASH confidential network logger Research prototype, Singapore AI Safety Hub (SASH)
• Operational use TOPLOC Open-source project, Prime Intellect

On-chip telemetry from timing, memory and performance counters

None on the map

1. Proof-of-Guardrail in AI Agents and What (Not) to Trust from It, X. Jin et al. (2026). Original
2. Verifiable-ClawGuard: proof-of-guardrail reference code, SaharaLabsAI (2026). Original
3. Safety Without Compromising on Privacy, D. McCann-Sayles et al. (2026). Original
4. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
5. Enabling Verifiably-Scoped Monitoring through Large Language Models and Trusted Compute, B. Penchas et al. (2026). Original
6. Auditor-in-a-Box: Tools for Third-Party Auditing, R. Rinberg & B. Penchas (2026). Original
7. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
8. DDRop: Active Memory Interposer Attacks on Confidential VMs by Dropping DDR5 Writes, J. De Meulemeester et al. (2026). Original
9. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
10. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
11. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
12. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
13. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
14. Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors, N. Cankaya et al. (2026). Original
15. Bit-Exact AI Inference Verification Without Performance Tradeoffs, N. Cankaya (2026). Original
16. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
17. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
18. Example Schemes for Verifying High-Stakes AI Agreements, Amodo Design (2026). Original
19. TOPLOC: A Locality Sensitive Hashing Scheme for Trustless Verifiable Inference, J. M. Ong et al. (2025). Original
20. DiFR: Inference Verification Despite Nondeterminism, A. Karvonen et al. (2025). Original
21. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
22. Guaranteeable Memory: An HBM-Based Chiplet for Verifiable AI Workloads, J. Petrie (2025). Original
23. Detecting Hidden ML Training With Zero-Overhead Telemetry, R. Rahman & S. Tajdari (2026). Original
24. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original
25. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original
26. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original