Proposal Explorer

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Excluded by your filters: Model identity attestation and Hardware-enabled guarantees (flexHEG) and guarantee processors

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Model identity attestation, Attestable Audits: Analysis · excluded by filters
• Hardware-enabled guarantees (flexHEG) and guarantee processors: Analysis · excluded by filters

Excluded by your filters

• Model identity attestation Readiness R2 is below the minimum of R3.
• Hardware-enabled guarantees (flexHEG) and guarantee processors Readiness R1 is below the minimum of R3.

Family findings

• Model identity attestation

  Context for Attestable Audits. These findings concern the family or other implementations; applicability must be checked against their stated scope.

  • Underlying attestation can be forged or relayed in Model identity attestation

    Critical for the enclave route against an operator with physical access to affected hardware, or control of an unpatched SEV-SNP hypervisor. It does not apply to the recomputation route. PAL*M excludes physical attacks, and Tinfoil acknowledges this boundary.

    The enclave route inherits the platform-specific TEE attestation failures. Intel TDX forgery and H100 relay were demonstrated with physical access and host control. Battering RAM defeated AMD SEV-SNP attestation on DDR4 servers; RMPocalypse did so from malicious host software on platforms without AMD's fixes. These demonstrate failures of the trust roots, not of each model-commitment protocol. ^{3 4 5 6 7 8}

    Response: The TEE.fail authors report that physical interposer attacks are outside Intel's and AMD's threat models. AMD reports fixes for RMPocalypse.

    Demonstrated attack · Critical · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

    Related mechanism R1 Hardware-enabled guarantees (flexHEG) and guarantee processors: A tamper-protected enclosure around the chip is the proposed answer when the party that holds the hardware may attack it physically. A pointer, not evidence that this flaw is mitigated. In the proposal.

  • Launch-state attestation does not by itself cover weights loaded later in Model identity attestation

    Attestation measures launch state, and weights are read from disk after boot. A signature checked at load time does not stop a malicious hypervisor from altering the disk afterwards. Tinfoil reports mitigating this with dm-verity checks on every read. Unmeasured runtime configuration remains a general risk. ^{9 10}

    Theoretical argument · Significant · Mitigated. On the record

  • For private models, a user can confirm consistency but not content in Model identity attestation

    When weights are not published, users can check that the same root hash is served each time, but not what the model is. Pairing the hash with an attested evaluation, as in Attestable Audits, is one proposed remedy. ^{1 9}

    Open question · Significant · Open. On the record

  • Recomputation depends on trusted logging and randomness, and its tolerance leaves a covert channel in Model identity attestation

    The recomputation variant assumes that every input, output and seed is logged correctly, and that the attacker can neither predict nor manipulate which messages are sampled for verification. Legitimate nondeterminism concentrates at a few token positions, and slow leaks within the tolerated slack remain possible. An independent study showed that an adversary who controls the prompts roughly doubles the bits leaked per token, reducing the exfiltration slowdown from 146–254 times under benign prompts to 60–118 times. The attack targets the exfiltration bound, not the check that outputs match the declared model. ^{11 12}

    Demonstrated attack · Significant · Open. On the record

    Related mechanism R1 Network taps and certifiers: Taps are proposed to copy and hash traffic on the monitored links, reducing reliance on the prover's own log. This still depends on the monitored boundary and trusted capture. A pointer, not evidence that this flaw is mitigated. Add

    Related mechanism R3 Deterministic and bit-exact inference: Bit-exact inference would remove the numerical tolerance that leaves this channel. A pointer, not evidence that this flaw is mitigated. Add

Open significant flaws

8 flaws in 2 mechanisms

• Relies on the TEE vendor and inherits TEE attacks in Attestable Audits

  The prototype trusts AWS Nitro, not the Intel TDX or AMD SEV-SNP attestation roots targeted by the cited confidential-VM studies. Those studies are class context, not a demonstrated attack on this Nitro prototype.

  The design depends on trusting the TEE vendor, AWS in the prototype. The authors cite memory-aliasing, ciphertext side-channel and malicious-interrupt attacks on confidential VMs (BadRAM, CIPHERLEAKS, Heckler). Their answer is to revoke vulnerable base images once such attacks are discovered. ¹

  Response: The authors propose revoking vulnerable base images; they do not report a red-team evaluation of the prototype.

  Theoretical argument · Significant · Open · Inherited finding. On the record · Related finding in TEE remote attestation for AI workloads

• Prompt-based model exfiltration is a residual gap in Attestable Audits

  The authors state that "prompt-based model exfiltration during the user interaction step remains a residual gap". ¹

  Open question · Significant · Open. On the record

• State attackers can likely defeat current secure enclosures in Hardware-enabled guarantees (flexHEG) and guarantee processors

  The flexHEG authors write that "nation-state attackers can likely compromise the best current secure enclosures", and that the marginal cost of circumvention per device is hard to estimate. RAND similarly judges that anti-tamper measures "would not be insurmountable for a determined and well-resourced adversary", although they raise costs and can reveal tampering. ^{14 16}

  Theoretical argument · Significant · Open. On the record

• Firmware-only retrofits rely on Secure Boot, which fault injection can bypass in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Part II notes that the most common attack on Secure Boot replaces the firmware and applies a voltage glitch while the signature is being checked. It also notes that sophisticated actors may use microprobing or laser voltage probing to read key registers. ¹⁴

  Theoretical argument · Significant · Open. On the record

• Many important rules cannot be checked on-chip in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Malicious intent "is not a technical property observable on-chip", and misuse depends on what is done with a computation's results. A guarantee processor cannot easily tell whether a network is the whole system or one expert in a mixture-of-experts system. Part III judges that a fully local ruleset "may not be entirely feasible" for the same reason. ^{13 15}

  Theoretical argument · Significant · Open. On the record

• FLOP accounting can be laundered through external data in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Results of earlier or parallel workloads could be hidden in the "external data" fed to a device, which would falsify the total FLOP count unless the inputs are explained or time delays are imposed. ¹⁴

  Theoretical argument · Significant · Open. On the record

• Supply-chain diversion and hidden backdoors in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Components could be diverted before a guarantee processor is added, and backdoors could be introduced during design or manufacturing. Open-source designs and physical scans of randomly selected chips are proposed as countermeasures. Part III proposes international oversight of production and extensive testing of a random sample of finished devices. ^{14 15}

  Open question · Significant · Open. On the record

  Related mechanism R1 Chip registries and manufacturing records: Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors. A pointer, not evidence that this flaw is mitigated. Add

• Coverage stops at flexHEG-equipped chips in Hardware-enabled guarantees (flexHEG) and guarantee processors

  Motivated actors will always be able to use some compute that is not flexHEG-equipped. Recalling existing consumer GPUs would likely be impractical, and reaching perfect coverage, or conclusively proving that no secret government data centres exist, would be "practically quite difficult". ^{13 15}

  Open question · Significant · Open. On the record

  Related mechanism R1 Chip registries and manufacturing records: Accounts for which chips exist and who holds them. A pointer, not evidence that this flaw is mitigated. Add

  Related mechanism R1 Remote detection of data centres: Looks for undeclared facilities that hold other chips. A pointer, not evidence that this flaw is mitigated. Add

Open minor flaws

1 mechanism with minor findings

• CPU-only enclaves force small, quantized models and high cost in Attestable Audits

  Memory limits required 4-bit quantization, and the quantized model scored 51.4% on zero-shot MMLU. CPU inference cost 21.7 times as much per token as GPU inference, and the enclave roughly doubled the CPU cost. The authors wrote that H100 confidential computing had no multi-GPU support. NVIDIA's white paper of August 2025 describes a protected-PCIe mode that passes all eight GPUs of a Hopper HGX node to one confidential VM, with NVLink traffic unencrypted. ^{1 2}

  Open question · Minor · Open. On the record

Not yet demonstrated

R1 Hardware-enabled guarantees (flexHEG) and guarantee processors

Need new chip designs

Hardware-enabled guarantees (flexHEG) and guarantee processors

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R3 TEE remote attestation for AI workloads Add
  • Model identity attestation waits on it. The prototype needs porting to GPU confidential computing to handle larger models; the authors expect an overhead as small as 5 times there.
  • Hardware-enabled guarantees (flexHEG) and guarantee processors depends on it.
• R1 Chip registries and manufacturing records Add

  Excluded by filters: readiness R1

  • Bears on the open significant flaw “Supply-chain diversion and hidden backdoors” in Hardware-enabled guarantees (flexHEG) and guarantee processors. Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors.
  • Bears on the open significant flaw “Coverage stops at flexHEG-equipped chips” in Hardware-enabled guarantees (flexHEG) and guarantee processors. Accounts for which chips exist and who holds them.
  • Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it. Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities.
• R1 Remote detection of data centres Add

  Excluded by filters: readiness R1

  • Bears on the open significant flaw “Coverage stops at flexHEG-equipped chips” in Hardware-enabled guarantees (flexHEG) and guarantee processors. Looks for undeclared facilities that hold other chips.
• R2 Tamper evidence for verifier devices Add

  Excluded by filters: readiness R2

  • Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it. State-level attackers who hold the hardware can likely compromise the best current secure enclosures.

Missing prerequisites

• R3 TEE remote attestation for AI workloads needed by Model identity attestation and Hardware-enabled guarantees (flexHEG) and guarantee processors Add
• R1 Chip registries and manufacturing records needed by Hardware-enabled guarantees (flexHEG) and guarantee processors Add

Shared foundations

• TEE remote attestation for AI workloads relied on by Model identity attestation and Hardware-enabled guarantees (flexHEG) and guarantee processors

Blockers

7 blockers recorded

• Model identity attestation
  • The prototype needs porting to GPU confidential computing to handle larger models; the authors expect an overhead as small as 5 times there. Performance & compatibility. Waits on TEE remote attestation for AI workloads ¹
  • As of September 2026 no code has been released for the prototype. Adversarial validation ¹
• Hardware-enabled guarantees (flexHEG) and guarantee processors
  • Integrated flexHEG needs substantial help from the accelerator manufacturer, and the authors estimate 3.7–7.9 years, from when the manufacturer starts work, for such hardware to displace other accelerators in frontier development. Access & governance ¹⁴
  • State-level attackers who hold the hardware can likely compromise the best current secure enclosures. Hardware trust. Waits on Tamper evidence for verifier devices ^{14 16}
  • Rival states would need to trust the design and manufacture of guarantee processors and enclosures, for example through open design, redundant processors from each side or oversight of production. Hardware trust ^{13 15}
  • Restricting future rule updates would need a formal language for rules, which the authors judge most likely infeasible for early flexHEG versions. Protocol soundness ¹³
  • Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities. Coverage & hidden compute. Waits on Chip registries and manufacturing records ¹⁵

From the family or selected implementation's record. ?

Model weights

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Unspecified for Model identity attestation. Check the implementation record.

Inputs and outputs

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Unspecified for Model identity attestation. Check the implementation record.

Training data

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Unspecified for Model identity attestation. Check the implementation record.

Model identity attestation

• R2 Attestable Audits Research prototype, University of Cambridge
• R2 PAL*M Research prototype, University of Waterloo
• R3 Tinfoil model identity (Modelwrap) Product, Tinfoil

Hardware-enabled guarantees (flexHEG) and guarantee processors

None on the map

1. Attestable Audits: Verifiable AI Safety Benchmarks Using Trusted Execution Environments, C. Schnabl et al. (2025). Original
2. NVIDIA Secure AI with Blackwell and Hopper GPUs (White Paper), NVIDIA (2025). Original
3. TEE.fail: Breaking Trusted Execution Environments via DDR5 Memory Bus Interposition, J. Chuang et al. (2026). Original
4. Battering RAM: Low-Cost Interposer Attacks on Confidential Computing via Dynamic Memory Aliasing, J. De Meulemeester et al. (2026). Original
5. RMPocalypse: How a Catch-22 Breaks AMD SEV-SNP, B. Schlüter & S. Shinde (2025). Original
6. SEV-SNP RMP Initialization Vulnerability (AMD-SB-3020), AMD (2025). Original
7. A primer on secure enclaves, Tinfoil (2026). Original
8. PAL*M: Property Attestation for Large Generative Models, P. Chantasantitam et al. (2026). Original
9. How Tinfoil Proves Exactly What Model Is Running, Tinfoil Team (2026). Original
10. On TEEs for Privacy-Preserving Monitoring in AI Governance, Gloria Z (2026). Original
11. Verifying LLM Inference to Detect Model Weight Exfiltration, R. Rinberg et al. (2025). Original
12. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
13. Flexible Hardware-Enabled Guarantees for AI Compute, J. Petrie et al. (2025). Original
14. Technical Options for Flexible Hardware-Enabled Guarantees, J. Petrie & O. Aarne (2025). Original
15. International Security Applications of Flexible Hardware-Enabled Guarantees, O. Aarne & J. Petrie (2025). Original
16. Hardware-Enabled Governance Mechanisms: Developing Technical Solutions to Exempt Items Otherwise Classified Under Export Control Classification Numbers 3A090 and 4A090, G. Kulp et al. (2024). Original
17. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
18. Hardware-Enabled Mechanisms for Verifying Responsible AI Development, A. O'Gara et al. (2025). Original