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Timed challenge-response and memory-occupation challenges and Network taps and certifiers

No new hardware needed

Timed challenge-response and memory-occupation challenges

Failures since mitigated

• Verifier dictionary attacks on hashes in Network taps and certifiers ⁵

Attack testing records published testing for this use. It does not by itself show independent review, a formal proof or that a deployed system is secure.

• Timed challenge-response and memory-occupation challenges, VRAM-residency challenge: Analysis
• Network taps and certifiers: Analysis

Family findings

• Timed challenge-response and memory-occupation challenges

  Context for VRAM-residency challenge. Findings from the mechanism family appear here as context. They apply to an implementation only when its own record lists them, under the conditions stated there.

  • Timing-based software attestation has been broken in practice in Timed challenge-response and memory-occupation challenges

    Castelluccia et al. implemented two generic attacks, one based on a return-oriented rootkit and one on code compression, together with specific attacks on SWATT and ICE-based schemes, on commodity sensor nodes. They conclude that secure time-based attestation is "very difficult, if not impossible, to design correctly". The attacks target embedded schemes, not AI accelerators. ^{2 3}

    Response: Perrig and van Doorn, two of the designers of SWATT and ICE, replied in August 2010. They argue that the rootkit attack defeats a naive implementation, not a property the schemes claim, and that the SWATT attack was run on a re-implementation on a chip with eight times the program memory, where SWATT's own chip is almost always full of code. They accept that the attack on ICE works.

    Known failure · Demonstrated attack · Significant · Disputed. On the record

  • Remote memory narrows the timing margin in Timed challenge-response and memory-occupation challenges

    Data-centre remote memory access returns in about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview says verification of memory saturation depends on ruling out remote access by latency or physical disconnection. It names pre-staging data into local memory as the remaining evasion and proposes an unpredictable, capacity-filling challenge to close it. ⁴

    Known failure · Theoretical argument · Significant · Open. On the record

    Related mechanism Research demo Bandwidth limits and compartmentalization: Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced. A pointer, not evidence that this failure is mitigated. Add

  • Error rates not quantified in Timed challenge-response and memory-occupation challenges

    Monfared et al. show separable timing distributions. Their acceptance rule passes a GPU when its mean time per round stays at or below a chosen maximum, and an appendix outlines statistical tests for the proof-of-work puzzle. They leave hardware-specific threshold values to future work and report no false-positive or false-negative rates. ¹

    Open question · Open question. On the record

Open significant failures

2 failures in 1 mechanism

• Output nondeterminism leaves covert capacity in Network taps and certifiers

  Hashing cannot remove information hidden in the outputs themselves. The Secure Gateway Device paper estimates that about 0.1 bit per token remains even with seed-synchronized replay checks. For a 200k-GPU inference cluster at full load (2,000 tokens per GPU per second), that is about 40 Mbit/s of covert egress, enough to move a 1 TB model in under three days. The paper names this the core remaining challenge and points to deterministic replay or active scrubbing of hardware-induced entropy. An independent study found that an adversary who chooses the prompts roughly doubles the bits leaked per token under Gumbel-based inference verification; see Bounding unexplained information in outputs. ^{5 12}

  Known failure · Theoretical argument · Significant · Open. On the record

  Related mechanism Operational use Deterministic and bit-exact inference: Deterministic replay is one of the two remedies the flaw's source names. A pointer, not evidence that this failure is mitigated. Add

  Related mechanism Research demo Bounding unexplained information in outputs: Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict. A pointer, not evidence that this failure is mitigated. Add

• Residual side channels in simple passive setups in Network taps and certifiers

  Amodo's analysis of its own tapped prototype lists unvalidated header fields, timing of permitted traffic and variation in response formatting as residual channels, and concludes that the passive tap must be replaced by an active one. ⁸

  Known failure · Theoretical argument · Significant · Open. On the record

Scope limitations

• Answers are not tied to one GPU in VRAM-residency challenge

  The paper's floating-point fingerprint characterises a GPU model. The authors state that it does not distinguish individual GPUs, so a timely answer does not show which device of that model held the data. ¹

  Scope limitation · Theoretical argument. On the record

• Some links cannot be passively tapped in Network taps and certifiers

  Cankaya notes that copper-connected scale-up domains (for example NVL72 racks and TPU v7 cubes) are much harder to tap than fibre, and that optical budgets make passive taps impractical on 400GBASE-SR8 multimode links. Amodo found no taps advertised for 53 GBaud links as of May 2026. ^{6 13}

  Scope limitation · Open question. On the record

• Encrypted fabrics hide plaintext from both parties in Network taps and certifiers

  Cankaya notes that with TEE-protected sessions whose keys are ephemeral and managed inside the TEE, neither the operator nor the manufacturer can recover session keys after the session, so tapped traffic could not be opened for recomputation. For other encrypted fabrics, the operator can retain keys. ⁶

  Scope limitation · Open question. On the record

• Completeness rests on physical monitoring left out of scope in Network taps and certifiers

  The Secure Gateway Device paper assumes the facility is physically monitored, and states that the whole architecture depends on the device being the only communication channel. It names radio emanation, power-line signalling and thermal channels as covert channels beyond that scope. ⁵

  Scope limitation · Open question. On the record

  Related mechanism Proposed Side-channel suppression for isolated facilities: Addresses the radio, power-line and thermal channels that network-level designs leave out. A pointer, not evidence that this failure is mitigated. Add

Open questions

• Error rates not quantified in VRAM-residency challenge

  Monfared et al. report a timing gap of more than 350 ms but leave hardware-specific thresholds to future work and state that false-positive and false-negative rates are not quantified. ¹

  Open question · Open question. On the record

Not yet demonstrated

Proposed Network taps and certifiers

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• Operational use Deterministic and bit-exact inference Add
  • Bears on the open significant failure “Output nondeterminism leaves covert capacity” in Network taps and certifiers. Deterministic replay is one of the two remedies the flaw's source names.
  • Network taps and certifiers waits on it. Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove.
• Research demo Bounding unexplained information in outputs Add
  • Bears on the open significant failure “Output nondeterminism leaves covert capacity” in Network taps and certifiers. Bounds the hidden information outputs can carry by measuring what the declared computation fails to predict.
• Research demo Tamper evidence for verifier devices Add
  • Network taps and certifiers waits on it. Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them.
• Proposed Side-channel suppression for isolated facilities Add
  • Network taps and certifiers waits on it. Radio, power-line and thermal channels are not addressed by network-level designs.
• Operational use Sampled inference recomputation Add
  • Network taps and certifiers depends on it.

Missing prerequisites

• Operational use Sampled inference recomputation needed by Network taps and certifiers Add
• Operational use Deterministic and bit-exact inference needed by Network taps and certifiers Add
• Research demo Tamper evidence for verifier devices needed by Network taps and certifiers Add
• Proposed Side-channel suppression for isolated facilities needed by Network taps and certifiers Add

Blockers

7 blockers recorded

• Timed challenge-response and memory-occupation challenges
  • The challenge data occupies a large part of GPU memory for as long as the test runs. Performance & compatibility ¹
  • No test across servers has been reported, and the MIRI overview lists network-level probing of memory contents as undemonstrated. Adversarial validation ^{1 4}
• Network taps and certifiers
  • No complete verification tap has been demonstrated at production frontend link rates, and on the tested CPU no hash algorithm reached line rate with minimum-size frames. Performance & compatibility ^{13 14}
  • Nondeterministic inference leaves covert capacity in outputs that hashing cannot remove. Evidence binding. Waits on Deterministic and bit-exact inference ⁵
  • Taps and gateway devices need tamper-evident housing and physical monitoring so that traffic cannot bypass them. Hardware trust. Waits on Tamper evidence for verifier devices ^{4 5}
  • Radio, power-line and thermal channels are not addressed by network-level designs. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ⁵
  • Red-teaming by specialists is called for but has not been reported. Adversarial validation ⁵

From the family or selected implementation's record. ?

Model weights

Depends on the design for Network taps and certifiers.

Unspecified for Timed challenge-response and memory-occupation challenges. Check the implementation record.

Inputs and outputs

Depends on the design for Network taps and certifiers.

Unspecified for Timed challenge-response and memory-occupation challenges. Check the implementation record.

Training data

Depends on the design for Network taps and certifiers.

Unspecified for Timed challenge-response and memory-occupation challenges. Check the implementation record.

Timed challenge-response and memory-occupation challenges

• Proposed Data-centre memory challenging Proposed architecture, Machine Intelligence Research Institute
• Research demo GPU contention probes Research prototype
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Research demo SAGE Research prototype
• Research demo VRAM-residency challenge Research prototype

Network taps and certifiers

• Proposed AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• Proposed Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• Proposed SASH confidential network logger Research prototype, Singapore AI Safety Hub (SASH)

1. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
2. On the Difficulty of Software-Based Attestation of Embedded Devices, C. Castelluccia et al. (2009). Original
3. Refutation of "On the Difficulty of Software-Based Attestation of Embedded Devices", A. Perrig & L. van Doorn (2010). Original
4. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
5. Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors, N. Cankaya et al. (2026). Original
6. The Fundamentals and Feasibility of Secure Network Taps for Verifying AI Datacenter Use, N. Cankaya (2026). Original
7. Verification Plan, R. Dean (2026). Original
8. Fitting a Network TAP to our Inference Verification Prototype, Amodo Design (2026). Original
9. Amodo-Design/Inference-Recomputation-Prototype (GitHub repository), Amodo Design (2026). Original
10. inference-verification: Inference Verification Prototype, Singapore AI Safety Hub (SASH) (2026). Original
11. Internationalising AI Verification, Singapore AI Safety Hub (SASH) (2026). Original
12. Adversarial Entropy Inflation Against Gumbel-Based Inference Verification, N. Kezins (2026). Original
13. Network Tapping for AI Verification: A Technical Assessment, Amodo Design (2026). Original
14. Network Traffic Hashing, Amodo Design (2026). Original