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A verification proposal from the AI Verification Tech Map, from its records of 2026-10-08. https://trustbutveri.fyi/explorer/?mechanisms=M-0022,M-0009&implementations=M-0022:I-0010

Claims

Mechanisms2

Analysis

Overview

Columns Claims Prover Attack testing Hardware Verifier sees
MechanismReadinessOpen flaws
Side-channel suppression for isolated facilitiesRAND secure inference data center (SIDC) design R111Family context below
Hardware-enabled guarantees (flexHEG) and guarantee processors R16
  • Open flaws: n critical n significant n minor
Claim coverageNo claims yet

Add claims to see which ones the mechanisms address.

Properties1 built for an adversarial prover
Attack testing2 mechanisms with published testing

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

Limits1 family with findings to check · 2 not yet demonstrated · 2 mechanisms with open significant findings
Family findings
  • Side-channel suppression for isolated facilities

    Context for RAND secure inference data center (SIDC) design. These findings concern the family or other implementations; applicability must be checked against their stated scope.

    • Supply-chain implants may evade inspection in Side-channel suppression for isolated facilities

      Cankaya identifies malicious hardware embedded deep in purchased components as a residual risk that visual inspection and disassembly may not catch. He notes that radiographic examination under high-security standards could mitigate it. 2

      Theoretical argument · Significant · Open. On the record

    • Openings for airflow, power and optics weaken shielding in Side-channel suppression for isolated facilities

      Cankaya notes that keeping attenuation high while passing high-power airflow, cabling and optical links adds complexity beyond existing shielded-enclosure specifications. 2

      Theoretical argument · Significant · Open. On the record

    • Inspection assumptions may not hold in Side-channel suppression for isolated facilities

      The design's statistical argument assumes that visual or disassembly inspection catches every flaw that is present in a sampled unit. Cankaya is unsure whether destructive teardowns are defence-dominant or offence-dominant. 2

      Open question · Significant · Open. On the record

Open significant flaws
7 flaws in 2 mechanisms
  • Everything rests on the trusted setup in RAND secure inference data center (SIDC) design

    Reference measurements for model weights and reference data are established in a trusted setup phase. The report states that the system cannot detect compromise that happened before ingestion if the trusted setup itself is compromised. 1

    Theoretical argument · Significant · Open. On the record

  • State attackers can likely defeat current secure enclosures in Hardware-enabled guarantees (flexHEG) and guarantee processors

    The flexHEG authors write that "nation-state attackers can likely compromise the best current secure enclosures", and that the marginal cost of circumvention per device is hard to estimate. RAND similarly judges that anti-tamper measures "would not be insurmountable for a determined and well-resourced adversary", although they raise costs and can reveal tampering. 4 6

    Theoretical argument · Significant · Open. On the record

  • Firmware-only retrofits rely on Secure Boot, which fault injection can bypass in Hardware-enabled guarantees (flexHEG) and guarantee processors

    Part II notes that the most common attack on Secure Boot replaces the firmware and applies a voltage glitch while the signature is being checked. It also notes that sophisticated actors may use microprobing or laser voltage probing to read key registers. 4

    Theoretical argument · Significant · Open. On the record

  • Many important rules cannot be checked on-chip in Hardware-enabled guarantees (flexHEG) and guarantee processors

    Malicious intent "is not a technical property observable on-chip", and misuse depends on what is done with a computation's results. A guarantee processor cannot easily tell whether a network is the whole system or one expert in a mixture-of-experts system. Part III judges that a fully local ruleset "may not be entirely feasible" for the same reason. 3 5

    Theoretical argument · Significant · Open. On the record

  • FLOP accounting can be laundered through external data in Hardware-enabled guarantees (flexHEG) and guarantee processors

    Results of earlier or parallel workloads could be hidden in the "external data" fed to a device, which would falsify the total FLOP count unless the inputs are explained or time delays are imposed. 4

    Theoretical argument · Significant · Open. On the record

  • Supply-chain diversion and hidden backdoors in Hardware-enabled guarantees (flexHEG) and guarantee processors

    Components could be diverted before a guarantee processor is added, and backdoors could be introduced during design or manufacturing. Open-source designs and physical scans of randomly selected chips are proposed as countermeasures. Part III proposes international oversight of production and extensive testing of a random sample of finished devices. 4 5

    Open question · Significant · Open. On the record

    Related mechanism R1 Chip registries and manufacturing records: Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors. A pointer, not evidence that this flaw is mitigated. Add

  • Coverage stops at flexHEG-equipped chips in Hardware-enabled guarantees (flexHEG) and guarantee processors

    Motivated actors will always be able to use some compute that is not flexHEG-equipped. Recalling existing consumer GPUs would likely be impractical, and reaching perfect coverage, or conclusively proving that no secret government data centres exist, would be "practically quite difficult". 3 5

    Open question · Significant · Open. On the record

    Related mechanism R1 Chip registries and manufacturing records: Accounts for which chips exist and who holds them. A pointer, not evidence that this flaw is mitigated. Add

    Related mechanism R1 Remote detection of data centres: Looks for undeclared facilities that hold other chips. A pointer, not evidence that this flaw is mitigated. Add

Open minor flaws
1 mechanism with minor findings
  • Security weakens over long operation in RAND secure inference data center (SIDC) design

    The authors claim that the facility can withstand attacks at the OC5 level for a five-year operational period. They expect its ability to withstand long OC5 campaigns to become less robust the longer the facility remains in operation. 1

    Theoretical argument · Minor · Open. On the record

Possible additions2 for open flaws · 4 for dependencies

Mechanisms on the map that are not in the proposal. Pointers, not recommendations.

  • R1 Chip registries and manufacturing records Add
    • Bears on the open significant flaw “Supply-chain diversion and hidden backdoors” in Hardware-enabled guarantees (flexHEG) and guarantee processors. Records each chip's identity and owner from the fab onwards, which bears on diversion before a guarantee processor is fitted. It does not address hidden backdoors.
    • Bears on the open significant flaw “Coverage stops at flexHEG-equipped chips” in Hardware-enabled guarantees (flexHEG) and guarantee processors. Accounts for which chips exist and who holds them.
    • Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it. Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities.
  • R1 Remote detection of data centres Add
    • Bears on the open significant flaw “Coverage stops at flexHEG-equipped chips” in Hardware-enabled guarantees (flexHEG) and guarantee processors. Looks for undeclared facilities that hold other chips.
  • R2 Tamper evidence for verifier devices Add
    • Hardware-enabled guarantees (flexHEG) and guarantee processors waits on it. State-level attackers who hold the hardware can likely compromise the best current secure enclosures.
  • R3 Model identity attestation Add
    • Side-channel suppression for isolated facilities depends on it.
  • R3 TEE remote attestation for AI workloads Add
    • Hardware-enabled guarantees (flexHEG) and guarantee processors depends on it.
Dependencies3 missing prerequisites · 9 blockers
Missing prerequisites
Blockers
9 blockers recorded
  • Side-channel suppression for isolated facilities
    • No prototype exists; RAND recommends prototyping key security features and integration now. Adversarial validation 1
    • The report describes internal integrity checks, audit logging and accreditation, but no way for a party outside the operator to verify the facility's properties. Access & governance 1
    • Human review of every prompt and response makes each request take three to five minutes, with the review steps as the rate-limiting factor. Performance & compatibility 1
    • Detailed design information is withheld from the public report and is to be evaluated privately with stakeholders, which limits independent public scrutiny. Access & governance 1
  • Hardware-enabled guarantees (flexHEG) and guarantee processors
    • Integrated flexHEG needs substantial help from the accelerator manufacturer, and the authors estimate 3.7–7.9 years, from when the manufacturer starts work, for such hardware to displace other accelerators in frontier development. Access & governance 4
    • State-level attackers who hold the hardware can likely compromise the best current secure enclosures. Hardware trust. Waits on Tamper evidence for verifier devices 4 6
    • Rival states would need to trust the design and manufacture of guarantee processors and enclosures, for example through open design, redundant processors from each side or oversight of production. Hardware trust 3 5
    • Restricting future rule updates would need a formal language for rules, which the authors judge most likely infeasible for early flexHEG versions. Protocol soundness 3
    • Governing all relevant chips depends on knowing where they are, through chip registries and detection of undeclared facilities. Coverage & hidden compute. Waits on Chip registries and manufacturing records 5
What the verifier sees1 unspecified

From the family or selected implementation's record.

Model weights

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Inputs and outputs

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Training data

Hidden by Hardware-enabled guarantees (flexHEG) and guarantee processors.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Exposure notes
Implementations3 systems
Side-channel suppression for isolated facilities
Hardware-enabled guarantees (flexHEG) and guarantee processors
None on the map
Sources8 cited
  1. Highly Secure Inference Data Centers: A Vertically Integrated Strategy for Security Engineering, S. F. Comer et al. (2026). Original
  2. Suppressing Side Channels in an Untrusted Data Center via Retrofitted Defenses, N. Cankaya (2026). Original
  3. Flexible Hardware-Enabled Guarantees for AI Compute, J. Petrie et al. (2025). Original
  4. Technical Options for Flexible Hardware-Enabled Guarantees, J. Petrie & O. Aarne (2025). Original
  5. International Security Applications of Flexible Hardware-Enabled Guarantees, O. Aarne & J. Petrie (2025). Original
  6. Hardware-Enabled Governance Mechanisms: Developing Technical Solutions to Exempt Items Otherwise Classified Under Export Control Classification Numbers 3A090 and 4A090, G. Kulp et al. (2024). Original
  7. Secure, Governable Chips: Using On-Chip Mechanisms to Manage National Security Risks from AI & Advanced Computing, O. Aarne et al. (2024). Original
  8. Hardware-Enabled Mechanisms for Verifying Responsible AI Development, A. O'Gara et al. (2025). Original

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Filter mechanisms

Filters apply to mechanisms only. They describe the setting a proposal is for, and all are off by default. A mechanism that a filter rules out is flagged and does not count towards claim coverage. Selected implementations use their own record fields. A match means not excluded; conditional or unspecified exposure stays with a note. Passing a filter does not establish that the assumptions hold in a deployment.

All 25 mechanisms match.

Prover

How far can the party being checked be trusted?

The prover is the party being checked. Semi-trusted designs rely on part of its stack: usually the chip vendor's hardware root of trust, its firmware or counters, or its supply-chain records. Adversarial designs aim to hold even if it cheats wherever the checks allow, within their stated assumptions.

Keeps mechanisms whose threat model holds against at least this prover. Adversarial is the strongest assumption. Definitions

Verifier devices on site

May the verifier install its own hardware at the prover's sites?

Some mechanisms need a device the verifier owns or trusts at the prover's facility, such as a network tap, a bandwidth limiter or a sealed sensor. Choose Not allowed when the setting rules that out. Inspectors are not covered.

"Not allowed" removes mechanisms that need a retrofit device, such as a network tap or a sealed sensor. Definitions

Prover cooperation

How much must the prover take part?

Required: the prover takes part, for example by logging requests, producing proofs or opening records. Partial: some access, such as installing a device. Not required: works from outside, such as satellite imagery.

"Partial at most" removes mechanisms that need the prover's active participation. "Not required" keeps only those that work without it. Definitions

Chips

May the proposal depend on new chip designs?

New chip features take years to reach a deployed fleet and cover only chips made after they ship. Mechanisms that use shipping features, such as trusted execution environments or performance counters, stay.

"Existing chips only" removes mechanisms that need changes to future chip designs. Definitions

Minimum readiness

How mature must each mechanism be?

A level describes the public evidence for a mechanism's stated use, not its cost or feasibility. R3 can still have open critical flaws.

Keeps mechanisms whose readiness level is at least this one. Definitions

Attack testing

How hard has each mechanism been attacked in public?

The strongest published attempt to break the mechanism for its verification use: a security analysis, red-teaming by its developers or collaborators, or a red team independent of them.

Keeps mechanisms whose strongest published attack testing is at least this. Definitions

Keep hidden from the verifier

What must the verifier never see? Choose any.

Model weights: the checked model's parameters. Inputs and outputs: the requests a deployed model serves and its responses. Training data: what a model was trained on. Each mechanism's exposure is the editors' reading of its record: shown, depends on the design (kept, with a note), hidden, not involved, or unspecified for a selected implementation. Code and configuration are not covered yet.

Removes mechanisms that show the asset to the verifier. Conditional or unspecified exposure stays with a note and needs checking against the privacy requirement.

Claims

A claim is something one party wants to verify about another party's AI hardware or software. Each claim's number shows how the proposal addresses it.

  • Addressed. A mechanism in the proposal is aimed at this claim and is not excluded by the filters.
  • Partly addressed. Only supporting mechanisms, or mechanisms aimed at it that the filters exclude.
  • Unaddressed. No mechanism in the proposal addresses this claim.

Addressed means a mechanism in the proposal is aimed at the claim and is not excluded by your filters. It does not mean the claim is verified: check its assessed use, readiness, assumptions and open flaws.

All claims

Mechanisms

A mechanism is a general technique for verifying claims. Its badge is its readiness level for its stated use. An optional implementation choice narrows its assumptions, assessed use and claim links to that record. Lines join it to the claims it addresses. Click a line for details.Under its name it lists the claims it is aimed at or supports.

  • Aimed at the claim: verifying it is a direct purpose of the mechanism.
  • Supports the claim: helps verify it without being aimed at it.
  • Faint: excluded by your filters, so it does not count towards claim coverage.

All mechanisms

Overview

One row per mechanism in the proposal. Every mark comes from that mechanism's record, as listed in the panels below; what the verifier sees is the editors' reading of the record's text. Flaw counts are per mechanism. Summary counts name mechanisms with open findings, not a sum of attacks. Choosing an implementation narrows each row to that record's assessed use; family findings remain as context.

What the verifier sees

For model weights, inputs and outputs, and training data. This is the editors' reading of each mechanism's record (its threat model, how it works and its limitations), not a field of the record. Shown: the verifier sees it. Depends: on the design or variant, or the verifier sees only samples. Hidden: the verifier sees only commitments, hashes, proofs or results. Not involved: the record does not handle it. Unspecified: the selected implementation has no asset-specific assessment here.

Possible additions

Mechanisms on the map, not in the proposal, that the records connect to an unaddressed or partly addressed claim, an open flaw or a dependency. They are pointers, not recommendations: each brings its own readiness level and flaws, and none is claimed to close a flaw. Links from flaws are the editors' reading of the two records.

Start from a published design

Choosing a design loads the mechanisms its record realises or depends on. If the proposal has no claims yet, it also loads the claims that record says the design addresses.

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