Proposal Explorer

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Built for an adversarial prover

Bandwidth limits and compartmentalization, Side-channel suppression for isolated facilities and Timed challenge-response and memory-occupation challenges

No new hardware needed

Timed challenge-response and memory-occupation challenges

Published attempts to break a system, including those that found failures. Testing history does not show that open flaws are resolved.

• Bandwidth limits and compartmentalization: Analysis
• Side-channel suppression for isolated facilities, Low-trust AI compute verification system overview: Analysis
• Timed challenge-response and memory-occupation challenges: Analysis

Family findings

• Side-channel suppression for isolated facilities

  Context for Low-trust AI compute verification system overview. These findings concern the family or other implementations; applicability must be checked against their stated scope.

  • Supply-chain implants may evade inspection in Side-channel suppression for isolated facilities

    Cankaya identifies malicious hardware embedded deep in purchased components as a residual risk that visual inspection and disassembly may not catch. He notes that radiographic examination under high-security standards could mitigate it. ⁹

    Theoretical argument · Significant · Open. On the record

  • Openings for airflow, power and optics weaken shielding in Side-channel suppression for isolated facilities

    Cankaya notes that keeping attenuation high while passing high-power airflow, cabling and optical links adds complexity beyond existing shielded-enclosure specifications. ⁹

    Theoretical argument · Significant · Open. On the record

  • Inspection assumptions may not hold in Side-channel suppression for isolated facilities

    The design's statistical argument assumes that visual or disassembly inspection catches every flaw that is present in a sampled unit. Cankaya is unsure whether destructive teardowns are defence-dominant or offence-dominant. ⁹

    Open question · Significant · Open. On the record

Open significant flaws

8 flaws in 3 mechanisms

• Low-communication training reduces the bandwidth training needs in Bandwidth limits and compartmentalization

  DiLoCo matched fully synchronous training on 8 workers while communicating 500 times less. Rahman writes that this family of methods theoretically allows large-scale training with less than 100 Mbps. Lucid includes these methods in its bounds, but notes that extreme activation compression, architectures with unusually small inter-layer widths, or modular paradigms could erode the margin. ^{2 6 7}

  Theoretical argument · Significant · Open. On the record

• Operator control of pod routing collapses the bound in Bandwidth limits and compartmentalization

  Lucid's analysis finds that if the operator can freely assign pods to routers, it could dedicate a whole cell of 100 or more pods to one pipeline stage. The bound then falls to about 90–220x uncompressed and as low as about 25x with compression. The proposed mitigation, auditor-controlled random assignment that is periodically re-randomized, has not been implemented. ²

  Theoretical argument · Significant · Open. On the record

• Undeclared local storage raises per-pod capacity in Bandwidth limits and compartmentalization

  More memory or storage per pod helps an adversary. Lucid requires per-pod storage to be declared, capped and physically inspected. ²

  Theoretical argument · Significant · Open. On the record

• Training within one pod is not covered in Bandwidth limits and compartmentalization

  Lucid's bounds concern pre-training models larger than the pods are sized for. Training models that fit in one pod, fine-tuning and reinforcement-learning post-training within one pod are outside the modelled threat. ²

  Open question · Significant · Open. On the record

• Parallel scale-up switches are hard enforcement points in Bandwidth limits and compartmentalization

  In GB200 topologies, GPUs reach GPUs in other nodes through NVSwitches without a NIC on the path. Amodo notes that limits are hard to enforce there because many switches work in parallel, so compromising one or two would bypass the limit. ⁵

  Theoretical argument · Significant · Open. On the record

• Mismatches cannot be attributed to cheating or error in Low-trust AI compute verification system overview

  A failed hash or replay does not show whether it came from an evasion attempt, a random bit flip or an evaluation error. The author notes that if detected anomalies can plausibly be waved off as malfunctions, deterrence becomes less effective, so the parties need an agreed escalation procedure that ends in attribution. ³

  Theoretical argument · Significant · Open. On the record

• Inspector agents may be manipulable in Low-trust AI compute verification system overview

  Automated compliance screening with LLM-based inspector agents must resist prompt-injection attacks. Adversarially trained systems might hide malicious actions with steganography, which makes backdoor detection an open problem. ³

  Open question · Significant · Open. On the record

• Remote memory narrows the timing margin in Timed challenge-response and memory-occupation challenges

  Data-centre remote memory access returns in about 1–2 µs, against about 70–200 ns for local DRAM. The MIRI overview says verification of memory saturation depends on ruling out remote access by latency or physical disconnection. It adds that pre-staging data is ruled out only by unpredictable, capacity-filling challenges. ³

  Theoretical argument · Significant · Open. On the record

  Related mechanism R2 Bandwidth limits and compartmentalization: Physical disconnection is proposed to exclude remote memory between the separated groups during a challenge. It depends on the isolation boundary being enforced. A pointer, not evidence that this flaw is mitigated. In the proposal.

Open minor flaws

2 mechanisms with minor findings

• Deliberate faults leak a bit each in Low-trust AI compute verification system overview

  A malicious device can leak one bit by deliberately outputting a wrong result, which blocks a disclosure when the cross-comparison fails. The design therefore needs a pre-agreed budget of tolerated faults. ³

  Theoretical argument · Minor · Open. On the record

• Error rates not quantified in Timed challenge-response and memory-occupation challenges

  Monfared et al. show separable timing distributions but do not define thresholds or statistical tests, so false-positive and false-negative rates are not quantified. ¹⁰

  Open question · Minor · Open. On the record

Not yet demonstrated

R1 Side-channel suppression for isolated facilities

Mechanisms on the map that are not in the proposal. Pointers, not recommendations. ?

• R3 Deterministic and bit-exact inference Add
  • Side-channel suppression for isolated facilities waits on it. Exact replay needs complete hardware and software metadata, and the tolerable slowdown from emulation is an open question.
• R2 Tamper evidence for verifier devices Add
  • Bandwidth limits and compartmentalization waits on it. Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU.
  • Side-channel suppression for isolated facilities waits on it. Tamper-evident, rapidly mass-manufacturable and retrofittable enclosures for side-channel defence are an open research question, and physical security against covert communication in every monitored data centre is challenging.
• R1 Network taps and certifiers Add
  • Bandwidth limits and compartmentalization waits on it. The verifier must know that all traffic leaving a pod crosses the capped, monitored links.
  • Side-channel suppression for isolated facilities waits on it. Empirical feasibility of passive optical splitting at 53–112 GBaud under realistic conditions is an open question.

Missing prerequisites

• R2 Tamper evidence for verifier devices needed by Bandwidth limits and compartmentalization Add
• R1 Network taps and certifiers needed by Side-channel suppression for isolated facilities Add
• R3 Deterministic and bit-exact inference needed by Side-channel suppression for isolated facilities Add

Shared foundations

• Tamper evidence for verifier devices relied on by Bandwidth limits and compartmentalization and Side-channel suppression for isolated facilities
• Network taps and certifiers relied on by Bandwidth limits and compartmentalization and Side-channel suppression for isolated facilities

Blockers

13 blockers recorded

• Bandwidth limits and compartmentalization
  • No cap that a verifier can check has been implemented or red-teamed. Adversarial validation ²
  • The verifier must know that all traffic leaving a pod crosses the capped, monitored links. Coverage & hidden compute. Waits on Network taps and certifiers ³
  • Shaping devices and routing assignments must be trusted by both parties; Amodo has not yet fully analysed resilience to a compromised DPU. Hardware trust. Waits on Tamper evidence for verifier devices ^{2 5}
  • Advances in low-communication training could shrink the margin that the cap enforces. Capacity bounds ^{2 6 7}
• Side-channel suppression for isolated facilities
  • Empirical feasibility of passive optical splitting at 53–112 GBaud under realistic conditions is an open question. Performance & compatibility. Waits on Network taps and certifiers ³
  • Exact replay needs complete hardware and software metadata, and the tolerable slowdown from emulation is an open question. Performance & compatibility. Waits on Deterministic and bit-exact inference ³
  • Tamper-evident, rapidly mass-manufacturable and retrofittable enclosures for side-channel defence are an open research question, and physical security against covert communication in every monitored data centre is challenging. Hardware trust. Waits on Tamper evidence for verifier devices ³
  • A mass-manufacturable, good-enough side-channel defence, particularly power-line filtering, has not been constructed or red-teamed. Coverage & hidden compute. Waits on Side-channel suppression for isolated facilities ³
  • Distinguishing one server's DRAM contents from another's by challenge-response timing, and a general challenge-response protocol for diverse data types, are open. Coverage & hidden compute. Waits on Timed challenge-response and memory-occupation challenges ³
  • The threat model is under-developed and needs input from cybersecurity and AI threat-modelling experts. Adversarial validation ³
• Timed challenge-response and memory-occupation challenges
  • No network-level memory challenge across data-centre servers has been demonstrated. Adversarial validation ³
  • Challenges that fill memory displace workloads; filling a pod's volatile memory takes tens of minutes and SSDs take hours. Performance & compatibility ^{3 10}
  • Outside help, such as remote memory, must be excluded during challenges. Coverage & hidden compute. Waits on Bandwidth limits and compartmentalization ³

From the family or selected implementation's record. ?

Model weights

Not involved: Bandwidth limits and compartmentalization and Timed challenge-response and memory-occupation challenges.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Inputs and outputs

Not involved: Bandwidth limits and compartmentalization and Timed challenge-response and memory-occupation challenges.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Training data

Not involved: Bandwidth limits and compartmentalization and Timed challenge-response and memory-occupation challenges.

Unspecified for Side-channel suppression for isolated facilities. Check the implementation record.

Bandwidth limits and compartmentalization

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 RAND secure inference data center (SIDC) design Proposed architecture, RAND

Side-channel suppression for isolated facilities

• R1 AI 2040 inference-only verification stack Proposed architecture, AI Futures Project
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• R1 RAND secure inference data center (SIDC) design Proposed architecture, RAND

Timed challenge-response and memory-occupation challenges

• R1 Data-centre memory challenging Proposed architecture, Machine Intelligence Research Institute
• R2 GPU contention probes Research prototype
• R1 Low-trust AI compute verification system overview Proposed architecture, Machine Intelligence Research Institute
• R2 SAGE Research prototype
• R2 VRAM-residency challenge Research prototype

1. Verification Plan, R. Dean (2026). Original
2. Traffic Shaping for Workload Classification, Lucid Computing (2026). Original
3. A System Overview for Near-Term, Low-Trust AI Compute Verification, N. Cankaya (2026). Original
4. De-risking Interconnect Limits for AI Verification, A. Scher et al. (2026). Original
5. The Tray as a Bandwidth Boundary, Amodo Design (2026). Original
6. DiLoCo: Distributed Low-Communication Training of Language Models, A. Douillard et al. (2024). Original
7. Does Distributed Training Undermine Compute Governance?, R. Rahman (2026). Original
8. Fingerprinting All AI Cluster I/O Without Mutually Trusted Processors, N. Cankaya et al. (2026). Original
9. Suppressing Side Channels in an Untrusted Data Center via Retrofitted Defenses, N. Cankaya (2026). Original
10. Timing and Memory Telemetry on GPUs for AI Governance, S. K. Monfared et al. (2026). Original
11. SAGE: Software-based Attestation for GPU Execution, A. Ivanov et al. (2023). Original
12. SWATT: SoftWare-based ATTestation for Embedded Devices, A. Seshadri et al. (2004). Original
13. Proofs of Space, S. Dziembowski et al. (2015). Original
14. Secure Code Update for Embedded Devices via Proofs of Secure Erasure, D. Perito & G. Tsudik (2010). Original
15. Software-Based Memory Erasure with Relaxed Isolation Requirements, S. Bursuc et al. (2024). Original
16. On the Difficulty of Software-Based Attestation of Embedded Devices, C. Castelluccia et al. (2009). Original
17. Refutation of "On the Difficulty of Software-Based Attestation of Embedded Devices", A. Perrig & L. van Doorn (2010). Original